STRUCTURE AND METHOD FOR ADVANCED BULK FIN ISOLATION
First Claim
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1. A method for forming a semiconductor structure, said method comprising:
- providing a bulk silicon substrate comprising a device region for an n-type semiconductor device of a first conductivity type and another device region located adjacent to said device region for said n-type semiconductor device of said first conductivity type, wherein said another device region is for another semiconductor device having said second conductivity type;
recessing an exposed portion of said bulk silicon substrate in said device region to expose a sub-surface of said bulk silicon substrate, wherein a hard mask layer portion is present on said another device region during said recessing;
forming a semiconductor material stack of, from bottom to top, a semiconductor punch through stop layer containing at least one dopant of a second conductivity type which is opposite from said first conductivity type, a semiconductor diffusion barrier layer containing no n- or p-type dopant, and an epitaxial semiconductor layer on said sub-surface of said bulk silicon substrate; and
forming a plurality of semiconductor fins in said device region, wherein each semiconductor fin of said plurality of semiconductor fins comprises, from bottom to top, a remaining portion of said semiconductor punch through stop layer, a remaining portion of said semiconductor diffusion barrier, and a remaining portion of said epitaxial semiconductor layer.
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Abstract
A non-planar semiconductor structure containing semiconductor fins that are isolated from an underlying bulk silicon substrate by an epitaxial semiconductor stack is provided. The epitaxial semiconductor material stack that provides the isolation includes, from bottom to top, a semiconductor punch through stop containing at least one dopant of a conductivity type which differs from the conductivity type of the particular device region that the semiconductor fin is formed in, and a semiconductor diffusion barrier layer containing no n- or p-type dopant.
8 Citations
19 Claims
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1. A method for forming a semiconductor structure, said method comprising:
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providing a bulk silicon substrate comprising a device region for an n-type semiconductor device of a first conductivity type and another device region located adjacent to said device region for said n-type semiconductor device of said first conductivity type, wherein said another device region is for another semiconductor device having said second conductivity type; recessing an exposed portion of said bulk silicon substrate in said device region to expose a sub-surface of said bulk silicon substrate, wherein a hard mask layer portion is present on said another device region during said recessing; forming a semiconductor material stack of, from bottom to top, a semiconductor punch through stop layer containing at least one dopant of a second conductivity type which is opposite from said first conductivity type, a semiconductor diffusion barrier layer containing no n- or p-type dopant, and an epitaxial semiconductor layer on said sub-surface of said bulk silicon substrate; and forming a plurality of semiconductor fins in said device region, wherein each semiconductor fin of said plurality of semiconductor fins comprises, from bottom to top, a remaining portion of said semiconductor punch through stop layer, a remaining portion of said semiconductor diffusion barrier, and a remaining portion of said epitaxial semiconductor layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A semiconductor structure comprising:
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a bulk silicon substrate portion comprising a device region for an n-type semiconductor device of a first conductivity type; and a plurality of semiconductor fins in said device region and extending upward from said bulk silicon substrate portion, wherein each semiconductor fin of said plurality of semiconductor fins comprises, from bottom to top, a semiconductor punch through stop portion containing a dopant of the second conductivity type that is opposite from said first conductivity type, a semiconductor diffusion barrier portion containing no n- or p-type dopant, and an epitaxial semiconductor portion. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19)
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Specification