METHOD TO MAKE BURIED, HIGHLY CONDUCTIVE P-TYPE III-NITRIDE LAYERS

• US 20160197151A1
• Filed: 11/30/2015
• Published: 07/07/2016
• Est. Priority Date: 12/01/2014
• Status: Active Grant

• Current Assignee: Yale University
• Original Assignee: Yale University
• Inventors: Li, Yufeng, Zhang, Cheng, Park, Sung Hyun, Han, Jung
• Granted Patent: US 11,018,231 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/306 Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/31
• CPC Class Codes: H01L 21/3245 of AIIIBV compounds
• CPC Class Codes: H01L 29/15 Structures with periodic or quasi periodic potential variation, e.g. multiple quantum wells, superlattices such structures applied for the control of light G02F1/017, applied in semiconductor lasers H01S5/34
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/207 further characterised by the doping material H01L29/2006 takes precedence
• CPC Class Codes: H01L 29/88 Tunnel-effect diodes
• CPC Class Codes: H01L 2933/0016 relating to electrodes
• CPC Class Codes: H01L 31/03044 comprising a nitride compounds, e.g. GaN
• CPC Class Codes: H01L 31/035236 Superlattices; Multiple quantum well structures
• CPC Class Codes: H01L 31/036 characterised by their crystalline structure or particular orientation of the crystalline planes
• CPC Class Codes: H01L 31/0725 Multiple junction or tandem solar cells
• CPC Class Codes: H01L 31/0735 comprising only AIIIBV compound semiconductors, e.g. GaAs/AlGaAs or InP/GaInAs solar cells
• CPC Class Codes: H01L 31/1856 comprising nitride compounds, e.g. GaN
• CPC Class Codes: H01L 33/16 with a particular crystal structure or orientation, e.g. polycrystalline, amorphous or porous
• CPC Class Codes: H01L 33/32 containing nitrogen
• CPC Class Codes: H01L 33/40 Materials therefor
• CPC Class Codes: Y02E 10/544 Solar cells from Group III-V materials

Abstract

A conductive, porous gallium-nitride layer can be formed as an active layer in a multilayer structure adjacent to one or more p-type III-nitride layers, which may be buried in a multilayer stack of an integrated device. During an annealing process, dopant-bound atomic species in the p-type layers that might otherwise neutralize the dopants may dissociate and out-diffuse from the device through the porous layer. The release and removal of the neutralizing species may reduce layer resistance and improve device performance.

Claims

1. An integrated device comprising:

a substrate;

a first n-type layer formed from III-nitride material;

a first p-type layer formed from III-nitride material; and

a first conductive, porous layer formed from III-nitride material and located adjacent to the first p-type layer, wherein a portion of the first conductive, porous layer is exposed to an ambient.

2. The integrated device of claim 1, wherein the first p-type layer is formed in a multilayer stack in which there are additional layers formed above and below the first p-type layer.

3. The integrated device of claim 1, wherein the first p-type layer is formed as a top layer of a multilayer stack.

4. The integrated device of claim 1, wherein the first p-type layer and the first n-type layer form a first pn junction.

5. The integrated device of claim 4, further comprising a second pn junction formed above and in series with the first pn junction.

6. The integrated device of claim 5, further comprising a second p-type layer located adjacent to the first p-type layer, wherein the second p-type layer has a dopant density greater than a dopant density of the first p-type layer and wherein the first conductive, porous layer physically contacts the second p-type layer.

7. The integrated device of claim 6, wherein a thickness of the second p-type layer is less than 1 micron.

8. The integrated device of claim 1, wherein the first conductive, porous layer comprises gallium nitride and has a dopant density between approximately 5×

10¹⁸ cm<sup>−

3</sup> and approximately 2×

10²⁰ cm<sup>−

3</sup>.

9. The integrated device of claim 8, wherein a majority of pore diameters in the porous layer are between approximately 20 nm and approximately 150 nm.

10. The integrated device of claim 9, wherein a porosity of the porous layer is between approximately 10% and approximately 50%.

11. The integrated device of claim 1, wherein the first n-type layer extends over a larger region of the substrate than the first p-type layer.

12. The integrated device of claim 1, wherein the first n-type layer is located adjacent to the substrate, the first conductive, porous layer is located over the first n-type layer, and the first p-type layer is located over the first conductive, porous layer.

13. The integrated device of claim 1, further comprising:

a second n-type layer formed adjacent to the first conductive, porous layer;

a second conductive, porous layer formed adjacent to the second n-type layer; and

a second p-type layer formed adjacent to the second conductive, porous layer.

14. The integrated device of claim 1, wherein the first p-type layer and the first n-type layer form a pn junction in a cascaded tunnel junction light-emitting diode.

15. The integrated device of claim 1, wherein the first p-type layer and the first n-type layer form a pn junction in a tandem junction solar cell.

16. The integrated device of claim 1, wherein the first p-type layer and the first n-type layer form a pn junction in a transistor.

17. The integrated device of claim 1, wherein the first p-type layer and the first n-type layer form a pn junction in a diode.

18. A method for fabricating an integrated device, the method comprising:

forming a first n-type layer above a substrate from III-nitride material;

forming a first p-type layer adjacent to the first n-type layer from III-nitride material; and

forming a first conductive, porous layer adjacent to the first p-type layer from III-nitride material, wherein a portion of the first conductive, porous layer is exposed to an ambient.

19. The method of claim 18, further comprising thermally annealing the integrated device to dissociate and out-diffuse dopant-bound atomic species.

20. The method of claim 19, wherein an annealing temperature is between approximately 600°

C. and approximately 800°

C.

21. The method of claim 18, wherein forming the first conductive, porous layer comprises:

forming a gallium-nitride n-type layer with a doping concentration between approximately 5×

10¹⁸ cm<sup>−

3</sup> and approximately 2×

10²⁰ cm<sup>−

3</sup>;

etching the gallium-nitride n-type layer to form exposed sidewalls of the gallium-nitride n-type layer;

electrochemically and laterally etching the gallium-nitride n-type layer to form the first conductive, porous layer.

22. The method of claim 21, wherein the electrochemically and laterally etching comprises:

immersing the exposed sidewalls in an electrolyte of nitric acid; and

applying an electrical potential between the electrolyte and the exposed sidewalls.

23. The method of claim 22, wherein the nitric acid has a concentration between approximately 15 M and approximately 18 M and the electrical potential has a substantially constant value between approximately 1 volt and approximately 10 volts.

24. The method of claim 18, further comprising:

forming a second p-type layer adjacent to the first p-type layer before forming the first conductive, porous layer, wherein a thickness of the second p-type layer is less than 1 micron;

forming a second n-type layer adjacent to the first conductive, porous layer; and

forming a third p-type layer adjacent to the second n-type layer.

25. The method of claim 24, further comprising doping the second p-type layer to a density that is greater than a dopant density of the first p-type layer.

26. The method of claim 24, wherein the first p-type layer and the first n-type layer form a first pn junction, the third p-type layer and the second n-type layer form a second pn junction, and the second p-type layer forms a tunneling bather between the first pn junction and the second pn junction.

27. The method of claim 24, further comprising:

patterning a hard mask over the third p-type layer; and

transferring a pattern of the hard mask by anisotropically etching the third p-type layer, the second n-type layer, the first conductive, porous layer, the second p-type layer, and the first p-type layer.

28. The method of claim 27, wherein the anisotropic etching forms a mesa that includes at least one buried p-type layer.