FREQUENCY SYNTHESIZER AND METHOD CONTROLLING FREQUENCY SYNTHESIZER

• US 20160197601A1
• Filed: 12/18/2015
• Published: 07/07/2016
• Est. Priority Date: 01/02/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Jong-Won Choi, Joon-Hee Lee, Sang-Wook Han, Sung-Jun Lee
• Inventors: HAN, SANG-WOOK, LEE, SUNG-JUN, LEE, JOON-HEE, CHOI, JONG-WON
• Granted Patent: US 9,762,220 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03K 2005/00071 by adding capacitance as a load
• CPC Class Codes: H03K 2005/00273 using digital comparators
• CPC Class Codes: H03K 5/131 Digitally controlled
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 7/083 the reference signal being additionally directly applied to the generator
• CPC Class Codes: H03L 7/102 the additional signal being directly applied to the controlled loop oscillator
• CPC Class Codes: H03L 7/181 a numerical count result being used for locking the loop, the counter counting during fixed time intervals H03L7/1806 takes precedence
• CPC Class Codes: H03L 7/1974 for fractional frequency division

Abstract

A voltage controlled oscillator (VCO) in a frequency synthesizer generates an output signal having a target frequency by being coarse tuned in accordance with a channel code derived through a binary tree search. Thereafter, the output signal of the VCO may be further tuned using a phase lock loop (PLL) circuit. Each stage of the binary tree search includes a comparison step that determines a channel code bit, and another step that confirms that the channel code converges to a final channel code within an established stage range value.

Claims

1. A frequency synthesizer comprising:

an oscillator that generates an oscillation frequency corresponding to a channel code;

a frequency decider that determines the channel code on the basis of the oscillation frequency and a reference value corresponding to a target frequency, and corrects the channel code upon determining an error in the channel code; and

a phase locker that fine tunes the oscillation frequency to the target frequency.

2. The frequency synthesizer of claim 1, wherein the frequency decider uses a binary tree search to coarse tune the oscillation frequency, wherein each stage of the binary tree search generates a corresponding binary tree search result.

3. The frequency synthesizer of claim 2, wherein the frequency decider comprises:

a first comparator that compares an output value indicative of the oscillation frequency with the reference value during each stage of the binary tree search to generate a comparison signal;

a corrector that generates a correction signal by comparing, during each stage of the binary tree search, a difference value between the output value and the reference value with a stage range value, wherein upon determining that the difference value exceeds the range stage value, the correction signal indicates the error in the channel code; and

a channel code decider that determines the channel code in response to the comparison signal and the correction signal.

4. The frequency synthesizer of claim 3, wherein the frequency decider further comprises a control unit that provides the reference value to the first comparator and the corrector.

5. The frequency synthesizer of claim 4, further comprising a counter that receives the oscillation frequency and generates a count value as the output value.

6. The frequency synthesizer of claim 5, wherein the corrector comprises:

a subtractor that receives the count value and the reference value and generates the different value; and

a second comparator that receives the difference value and stage range value and generates the correction signal.

7. The frequency synthesizer of claim 6, wherein the correction signal is provided to at least one of the channel code decider and control unit.

8. The frequency synthesizer of claim 7, wherein the control unit, upon receiving the correction signal indicating the error in the channel code, causes the channel code decider to nullify at least one binary tree search result.

9. The frequency synthesizer of claim 8, wherein the channel code decider inverts the at least one channel code bit upon nullifying the at least one binary tree search result.

10. The frequency synthesizer of claim 8, wherein the control unit causes the channel code decider to re-execute at least one stage of the binary tree search.

11. The frequency synthesizer of claim 3, wherein the oscillator is a voltage control oscillator (VCO) including a capacitor bank array, and the frequency decider is an Auto Bank Calibration (ABC) unit that applies the channel code to the capacitor bank array to control the generation of the oscillation frequency.

12. The frequency synthesizer of claim 8, wherein the channel code decider determines the channel code on a channel code bit-by-channel code bit basis,

each successively decided channel code bit is a binary tree search result determined by a corresponding stage of the binary tree search, and

the control unit nullifies the at least one binary tree search result by causing a most recently determined channel code bit to be re-determined by re-executing a corresponding stage of the binary tree search.

13. The frequency synthesizer of claim 8, wherein the channel code decider determines the channel code on a channel code bit-by-channel code bit basis,

each successively decided channel code bit is a binary tree search result determined by a corresponding stage of the binary tree search, and

the control unit nullifies the at least one binary tree search result by inverting a most recently determined channel code bit.

14. A frequency synthesizer that provides an output signal having a target frequency and comprises:

a voltage control oscillator (VCO) that generates the output signal;

a first tuning loop that coarse tunes the output signal to an intermediate frequency in response to a channel code selected on the basis of the target frequency, wherein the first tuning loop is configured to correct an error in a determination of the channel code during the coarse tuning; and

a second tuning loop that fine tunes the output signal from the intermediate frequency to the target frequency following completion of the first tuning loop.

15. The frequency synthesizer of claim 14, wherein the VCO is tunable over a broad range of frequencies including a plurality of intermediate frequencies, each intermediate frequency being uniquely associated with one of a plurality of channel codes.

16. The frequency synthesizer of claim 14, wherein the first tuning loop comprises a channel code decider that determines the channel code using a binary tree search.

17. The frequency synthesizer of claim 16, wherein the first tuning loop further comprises:

a control unit that provides a stage range value for reach stage of the binary tree search, and provides a reference value in response to the target frequency;

a prescaler that receives the output signal and converts the output signal to a scaled signal;

a counter that receives the scaled signal and generates a count value indicative of a frequency of the output signal;

a first comparator that receives the count value and the reference value and generates a comparison signal;

a corrector that generates a difference value from the count value and reference value and compares the difference value to the stage range value to generate a correction signal,

wherein the channel code decider determines the channel code in response to the comparison signal and the correction signal.

18. The frequency synthesizer of claim 14, wherein the second tuning loop comprises a phase lock loop (PLL) circuit.

19. A frequency synthesizer comprising:

of frequencies including a plurality of intermediate frequencies, wherein the plurality of intermediate frequencies correspond one-for-one with a plurality of channel codes;

a frequency decider that, upon receiving an instruction identifying a target frequency for the VCO, controls a coarse tuning step of the VCO, such that the VCO generates an output signal having a desired intermediate frequency among the plurality of intermediate frequencies, wherein the coarse tuning step generates a comparison signal by comparing a reference value corresponding to the target frequency and an output signal indicative of the output signal and generates a correction signal by determining whether a difference value between the reference value and the output value exceeds a stage range value, such that the frequency decider traverses a binary search tree generated in accordance with the plurality of channel codes in response to the comparison signal and the correction signal.

20. The frequency synthesizer of claim 19, wherein the frequency decider traverses the binary search tree stage by stage, each stage of the binary tree search determining at least one bit of a final channel code corresponding to the desired intermediate frequency.