LOW DROPOUT VOLTAGE REGULATOR INTEGRATED WITH DIGITAL POWER GATE DRIVER

• US 20160202714A1
• Filed: 09/26/2013
• Published: 07/14/2016
• Est. Priority Date: 09/26/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: LURIA, Kosta, ZELIKSON, Michael, LYAKHOV, Alexander, SHOR, Joseph
• Granted Patent: US 10,156,859 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G05F 1/56 using semiconductor devices in series with the load as final control devices G05F1/461 takes precedence
• CPC Class Codes: G06F 1/266 Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
• CPC Class Codes: H02M 1/0045 Converters combining the concepts of switch-mode regulation and linear regulation, e.g. linear pre-regulator to switching converter, linear and switching converter in parallel, same converter or same transistor operating either in linear or switching mode
• CPC Class Codes: H02M 1/088 for the simultaneous control of series or parallel connected semiconductor devices

Abstract

Described is an apparatus which comprises: a first power supply node to supply input power supply; a power transistor coupled to the first power supply node; a multiplexer to selectively control gate terminal of the power transistor according to whether the power transistor is to operate as part of a low dropout voltage regulator (LDO-VR) or is to operate as a digital switch; and a second power supply node coupled to the power transistor, the second power supply node to provide power supply to a load from the power transistor.

Claims

1. An apparatus comprising:

a first power supply node to supply input power supply;

a power transistor coupled to the first power supply node;

a multiplexer to selectively control gate terminal of the power transistor according to whether the power transistor is to operate as part of a low dropout voltage regulator (LDO-VR) or is to operate as a digital switch; and

a second power supply node coupled to the power transistor to provide power supply to a load from the power transistor.

2. The apparatus of claim 1, wherein the LDO-VR is of a flipped source follower type.

3. The apparatus of claim 2, wherein the LDO-VR comprises a diode connected transistor coupled to the first power supply node and another node.

4. The apparatus of claim 3, wherein the other node is coupled to the gate terminal of the power transistor via the multiplexer.

5. The apparatus of claim 4, wherein the LDO-VR comprises a capacitive multiplication compensation network coupled to the other node.

6. The apparatus of claim 3, wherein the diode to compensate pole movement during current demand change on the second power supply node.

7. The apparatus of claim 3, wherein the LDO-VR comprises:

a first p-type transistor with a source terminal coupled to the second power supply node; and

an amplifier or comparator to compare a reference with a divided down voltage on the second power supply node, the amplifier or comparator having an output to control gate terminal of the p-type transistor.

8. The apparatus of claim 7, wherein the LDO-VR further comprises:

a first n-type transistor coupled in series with the first p-type transistor, the first n-type transistor having a gate terminal controllable by a first bias voltage; and

a second n-type transistor coupled to drain terminals of the first p-type transistor and the first n-type transistor, the second n-type transistor having a gate terminal controllable by a second bias voltage.

9. The apparatus of claim 8, wherein the LDO-VR further comprises:

a resistor with a first terminal to receive a third bias voltage, and a second terminal;

a capacitor with a first terminal coupled to the second terminal of the resistor, the capacitor having a second terminal coupled to the other node which is coupled to the gate terminal of the power transistor via the multiplexer; and

a second p-type transistor coupled in series with the second n-type transistor, the second p-type transistor having a gate terminal coupled to the second terminal of the resistor and the first terminal of the capacitor.

10. The apparatus of claim 1, wherein the power transistor is a p-type transistor.

11. An apparatus comprising:

a power transistor to selectively operate as a digital power gate or as part of a low dropout voltage regulator (LDO-VR).

12. The apparatus of claim 11, wherein the LDO-VR is a flipped source follower type.

13. The apparatus of claim 11, wherein the power transistor is a p-type transistor.

14. The apparatus of claim 11, wherein the LDO-VR comprises a diode connected transistor to selectively couple to the power transistor.

15. The apparatus of claim 14, wherein the diode connected transistor to stabilize the LDO-VR at high current loads.

16. The apparatus of claim 14, wherein the diode connected transistor is a p-type transistor.

17. The apparatus of claim 11, wherein the LDO-VR comprises a capacitive multiplication compensation network to selectively couple to the power transistor.

18. The apparatus of claim 11, wherein the power transistor includes:

a gate terminal coupled to a multiplexer;

a source terminal coupled to a first power supply node; and

a drain terminal coupled to a second power supply node, the second power supply node for providing power to a load.

19. A system comprising:

a memory unit;

a processor coupled to the memory unit, the processor having an apparatus which comprises a power transistor to selectively operate as a digital power gate or as part of a low dropout voltage regulator (LDO-VR); and

a wireless interface for communicatively coupling the processor to another device.

21. The system of claim 19 further comprises a display unit for displaying content processed by the processor.

20. (canceled)