SYSTEM AND METHOD FOR MEMORY COMMAND QUEUE MANAGEMENT AND CONFIGURABLE MEMORY STATUS CHECKING
First Claim
1. An integrated circuit chip comprising:
- a memory;
a command receipt module configured to receive commands from a controller of a memory system;
a command queue module configured to maintain a list of the commands; and
a poll response module configured to send part or all of the list of commands in response to receipt of a poll command from the controller.
2 Assignments
0 Petitions
Accused Products
Abstract
Systems, apparatuses, and methods for command queue management and configurable memory status in a memory. A memory may include a controller and one or more memory integrated circuit chips, which each include memory arrays. The controller may send commands, such as read or write commands, to the one or more memory integrated circuit chips. The memory integrated circuit chips may maintain a command queue of the commands sent from the controller, thereby relieving the controller from such responsibility. Further, the memory integrated circuit chips may send an indication of an error in executing the commands, thereby relieving the controller from constant polling of the memory integrated circuit chips as to status.
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Citations
23 Claims
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1. An integrated circuit chip comprising:
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a memory; a command receipt module configured to receive commands from a controller of a memory system; a command queue module configured to maintain a list of the commands; and a poll response module configured to send part or all of the list of commands in response to receipt of a poll command from the controller. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A controller for a memory system comprising:
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a communication module configured to communicate with one or more memory integrated circuit chips; command generation module configured to generate and send, via the communication module, one or more commands to a memory integrated circuit chip; and error determination module configured to receive, via the communication module, a communication indicative of an error and to determine, based on the communication, whether an error has occurred in execution of any of the one or more commands, wherein the communication is not in response to polling by the controller of the memory integrated circuit chip. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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18. An integrated circuit chip comprising:
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a memory; a command receipt module configured to receive a command from a controller of a memory system; an execution module configured to execute the command received via the command receipt module; an error determination module configured to determine an error in execution of the command; and a communication generator configured to, in response to the error determination module determining an error in execution of the command, generate and send a communication indicative to the controller that the error has occurred. - View Dependent Claims (19, 20, 21, 22, 23)
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Specification