SYSTEM AND METHOD FOR MEMORY COMMAND QUEUE MANAGEMENT AND CONFIGURABLE MEMORY STATUS CHECKING

• US 20160202914A1
• Filed: 01/13/2015
• Published: 07/14/2016
• Est. Priority Date: 01/13/2015
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Hsu, Jonathan, Tuers, Daniel, Kuo, Tien-chien
• Granted Patent: US 9,626,106 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06
• CPC Class Codes: G06F 11/079 Root cause analysis, i.e. error or fault diagnosis in a hardware test environment G06F11/22; in a software test environment G06F11/36
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0629 Configuration or reconfiguration of storage systems
• CPC Class Codes: G06F 3/0653 Monitoring storage devices or systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

Systems, apparatuses, and methods for command queue management and configurable memory status in a memory. A memory may include a controller and one or more memory integrated circuit chips, which each include memory arrays. The controller may send commands, such as read or write commands, to the one or more memory integrated circuit chips. The memory integrated circuit chips may maintain a command queue of the commands sent from the controller, thereby relieving the controller from such responsibility. Further, the memory integrated circuit chips may send an indication of an error in executing the commands, thereby relieving the controller from constant polling of the memory integrated circuit chips as to status.

Claims

1. An integrated circuit chip comprising:

a memory;

a command receipt module configured to receive commands from a controller of a memory system;

a command queue module configured to maintain a list of the commands; and

a poll response module configured to send part or all of the list of commands in response to receipt of a poll command from the controller.

2. The integrated circuit chip of claim 1, wherein the list is indicative of an order of execution of the commands.

3. The integrated circuit chip of claim 2, wherein the command queue module is further configured to rearrange the commands in the list of commands in response to suspending execution of one of the commands in order for the list to be indicative of the order of execution of the commands.

4. The integrated circuit chip of claim 1, further comprising a command status module configured to store a status associated with one or more commands in the list of commands.

5. The integrated circuit chip of claim 4, wherein the command status module is configured to store the status of each of the commands in the list of commands;

and

wherein the poll response module is further configured to send the status of each of the commands in the list of commands in response to receipt of the poll command from the controller.

6. The integrated circuit chip of claim 1, further comprising a command pass indication module configured to store a pass or fail indication associated with one or more commands in the list of commands.

7. The integrated circuit chip of claim 6, wherein the command pass indication module is configured to store the pass or fail indication of each of the commands in the list of commands;

and

wherein the poll response module is further configured to send the pass or fail indication of each of the commands in the list of commands in response to receipt of the poll command from the controller.

8. The integrated circuit chip of claim 1, wherein the command queue module is configured to store a predetermined number of the commands sent from the controller;

and

wherein the predetermined number is determined based on how many commands may be completed during a longest bus transaction with the controller of the memory system.

9. The integrated circuit chip of claim 8, wherein the commands in the list of commands are for execution on a first die in the memory system;

wherein the longest bus transaction comprises a longest time in which the controller communicates with another die in the memory system.

10. A controller for a memory system comprising:

a communication module configured to communicate with one or more memory integrated circuit chips;

command generation module configured to generate and send, via the communication module, one or more commands to a memory integrated circuit chip; and

error determination module configured to receive, via the communication module, a communication indicative of an error and to determine, based on the communication, whether an error has occurred in execution of any of the one or more commands,

wherein the communication is not in response to polling by the controller of the memory integrated circuit chip.

11. The controller of claim 10, wherein the communication comprises an indication whether at least a part of the memory integrated circuit chip is ready to accept an additional command.

12. The memory system controller of claim 11, wherein the error determination module is configured to determine, based on the communication, whether the error has occurred by:

determining whether the communication has been received for more than a predetermined period; and

in response to determining that the communication has been received for more than the predetermined period, determining that the error has occurred.

13. The memory system controller of claim 10, further comprising an interrupt module configured to, responsive to receipt of the communication, interrupt processing of the controller.

14. The memory system controller of claim 10, further comprising a poll module configured to, in response to the error determination module determining the error, poll the memory integrated circuit chip regarding the error.

15. The memory system controller of claim 14, further comprising an error identification module configured to, in response to the poll module polling the memory integrated circuit chip regarding the error, receive an identification of the command that resulted in the error.

16. The memory system controller of claim 15, wherein the error identification module is configured to receive the identification of the command that resulted in the error by:

receiving a list of commands in the queue of the memory integrated circuit chip, and a pass or failure indication for each of the commands in the list.

17. The memory system controller of claim 14, further comprising a command queue module configured to, in response to the poll module polling the memory integrated circuit chip regarding the error, receive a list of commands in the queue of the memory integrated circuit chip.

18. An integrated circuit chip comprising:

a memory;

a command receipt module configured to receive a command from a controller of a memory system;

an execution module configured to execute the command received via the command receipt module;

an error determination module configured to determine an error in execution of the command; and

a communication generator configured to, in response to the error determination module determining an error in execution of the command, generate and send a communication indicative to the controller that the error has occurred.

19. The integrated circuit chip of claim 18, wherein the communication comprises an indication whether at least a part of the memory integrated circuit chip is ready to accept an additional command.

20. The integrated circuit chip of claim 19, further comprising at least one line configured to send the communication to indicate readiness to accept the additional command;

and

wherein the communication, when sent on the at least one line for more than a predetermined time period, is indicative to the controller than the error has occurred.

21. The integrated circuit chip of claim 20, wherein the communication generator is configured to, in response to the error determination module determining the error, maintain sending the communication on the at least one line regardless of readiness to accept the additional command.

22. The integrated circuit chip of claim 18, further comprising at least one communication line dedicated to transmitting the communication.

23. The integrated circuit chip of claim 18, further comprising a plurality of data lines;

and

wherein the communication generator is configured to send the communication indicative to the controller that the error has occurred on one or more of the plurality of data lines.