INSTRUCTION STREAM TRACING OF MULTI-THREADED PROCESSORS

• US 20160203073A1
• Filed: 01/09/2015
• Published: 07/14/2016
• Est. Priority Date: 01/09/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Eisen, Lee E., Heller, Lisa C., Huffer, Michael T., Schwarz, Eric M.
• Granted Patent: US 9,996,354 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1405 at machine instruction level
• CPC Class Codes: G06F 11/3447 Performance evaluation by modeling
• CPC Class Codes: G06F 11/3612 by runtime analysis performance monitoring G06F11/3466
• CPC Class Codes: G06F 11/3636 by tracing the execution of the program
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/30141 Implementation provisions of register files, e.g. ports
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
• CPC Class Codes: G06F 9/4887 involving deadlines, e.g. rate based, periodic

Abstract

A method and apparatus for tracing instruction streams for a multi-threaded processor are disclosed herein. In one embodiment, the apparatus includes a last thread register configured to store a thread index that indicates a last executed thread, a tracing memory configured to store, within each of a plurality of storage locations, state information corresponding to a dispatch cycle for a multi-threaded processor, and a tracing control module configured to provide the state information to the tracing memory. The state information includes instruction information and a previous thread index. The state information may also include a flip bit that is used to determine a current insertion point within the tracing memory. A corresponding method is also disclosed herein.

Claims

1. A method for tracing instruction streams for a multi-threaded processor, the method comprising:

storing, within a last thread register, a thread index that indicates a last executed thread;

storing, within each of a plurality of storage locations within a tracing memory, state information corresponding to a dispatch cycle for a multi-threaded processor;

wherein the state information comprises a previous thread index.

2. The method of claim 1, wherein the state information comprises a flip bit that is used to determine a current insertion point within the tracing memory.

3. The method of claim 1, further comprising reconstructing state information for one or more threads from the state information within the tracing memory.

4. The method of claim 1, wherein the state information comprises instruction information.

5. The method of claim 4, wherein the instruction information corresponds to a group of instructions dispatched in the same cycle.

6. The method of claim 4, wherein the instruction information indicates an operation code.

7. The method of claim 6, wherein the operation code corresponds to one or more micro-operations.

8. The method of claim 1, wherein the state information comprises one or more of program counter information, an execution unit identifier, a register identifier, a group identifier, and a pipeline identifier.

9. The method of claim 1, wherein the tracing memory is partitioned into a plurality of partitions and wherein each partition of the plurality of partitions corresponds to a particular thread.

10. The method of claim 9, wherein the tracing memory is selectively partitioned into the plurality of partitions.

11. An apparatus for tracing instruction streams for a multi-threaded processor, the apparatus comprising:

a last thread register configured to store a thread index that indicates a last executed thread;

a tracing memory configured to store, within each of a plurality of storage locations, state information corresponding to a dispatch cycle for a multi-threaded processor;

a tracing control module configured to provide the state information to the tracing memory; and

wherein the state information comprises a previous thread index.

12. The apparatus of claim 11, wherein the state information comprises a flip bit that is used to determine a current insertion point within the tracing memory.

13. The apparatus of claim 11, wherein the state information comprises instruction information.

14. The apparatus of claim 13, wherein the instruction information corresponds to a group of instructions dispatched in the same cycle.

15. The apparatus of claim 13, wherein the instruction information indicates an operation code.

16. The apparatus of claim 15, wherein the operation code corresponds to one or more micro-operations.

17. The apparatus of claim 11, wherein the state information comprises one or more of program counter information, an execution unit identifier, a register identifier, a group identifier, and a pipeline identifier.

18. The apparatus of claim 11, wherein the tracing memory is partitioned into a plurality of partitions and wherein each partition of the plurality of partitions corresponds to a particular thread.

19. The apparatus of claim 18, wherein the tracing control module is configured to selectively partition the tracing memory into the plurality of partitions.

20. The apparatus of claim 11, further comprising at least one thread address counter configured to provide an address to the tracing memory.