METHODS FOR REDUCING CONGESTION REGION IN LAYOUT AREA OF IC
First Claim
1. A method for reducing congestion regions in a layout of an integrated circuit, comprising:
- obtaining a placement of the integrated circuit, wherein the placement comprises a first signal path between a first macro module and a second macro module, and the first signal path passes through a routing area of the placement for transmitting a specific signal;
identifying a congestion region of the routing area, wherein the first signal path comprises at least one cell or at least one routing path in the congestion region;
obtaining a cost evaluation for each candidate position of the routing area by moving the cell or the routing path out of the congestion region; and
moving the cell or the macro module corresponding to the routing path to the candidate position having a minimum cost evaluation among the cost evaluations, and simultaneously updating the placement and the routing paths according to the cell or the macro module moved to the candidate position having the minimum cost evaluation.
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Abstract
A method for reducing congestion regions of an integrated circuit is provided. A placement of the IC is obtained, wherein the placement includes a signal path between a first macro module and a second macro module. The signal path passes through a routing area of the placement for transmitting a specific signal. A congestion region of the routing area is identified. The signal path includes at least one cell or routing path in the congestion region. A cost evaluation is obtained for each candidate position of the routing area by moving the cell or the routing path out of the congestion region. The cell is moved to the candidate position having a minimum cost evaluation among the cost evaluations. The placement and the routing paths are simultaneously updated according to the cell moved to the candidate position having the minimum cost evaluation.
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Citations
28 Claims
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1. A method for reducing congestion regions in a layout of an integrated circuit, comprising:
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obtaining a placement of the integrated circuit, wherein the placement comprises a first signal path between a first macro module and a second macro module, and the first signal path passes through a routing area of the placement for transmitting a specific signal; identifying a congestion region of the routing area, wherein the first signal path comprises at least one cell or at least one routing path in the congestion region; obtaining a cost evaluation for each candidate position of the routing area by moving the cell or the routing path out of the congestion region; and moving the cell or the macro module corresponding to the routing path to the candidate position having a minimum cost evaluation among the cost evaluations, and simultaneously updating the placement and the routing paths according to the cell or the macro module moved to the candidate position having the minimum cost evaluation. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method for reducing congestion regions in a layout of an integrated circuit, comprising:
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obtaining a placement of the integrated circuit, wherein the placement comprises a first signal path between a first macro module and a second macro module; obtaining a congestion region of a routing area of the placement and a sparse region of the routing area adjacent to the congestion region, wherein the first signal path comprises at least one cell in the congestion region and a plurality of routing paths corresponding to the cell; obtaining a plurality of candidate positions within the sparse region, wherein each of the candidate positions is an unoccupied area capable of placing the cell; calculating a cost evaluation for each of the candidate positions by moving the cell from the congestion region to the candidate position; and simultaneously updating the placement and the routing paths according to a second signal path between the first macro module and the second macro module, wherein the second signal path comprises the cell moved to the candidate position having a minimum cost evaluation among the cost evaluations. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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21. A non-transitory computer-readable storage medium storing instructions that, when executed by a computer, cause the computer to perform a method for reducing congestion regions in a layout of an integrated circuit, the method comprising:
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obtaining a placement of the integrated circuit, wherein the placement comprises a first signal path between a first macro module and a second macro module, and the first signal path passes through a routing area of the placement for transmitting a specific signal; identifying a congestion region of the routing area, wherein the first signal path comprises at least one cell or at least one routing path in the congestion region; obtaining a cost evaluation for each candidate position of the routing area by moving the cell or the routing path of the congestion region; and moving the cell or the macro module corresponding to the routing path to the candidate position having a minimum cost evaluation among the cost evaluations, and simultaneously updating the placement and the routing paths according to the cell or the macro module moved to the candidate position having the minimum cost evaluation. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28)
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Specification