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METHODS FOR REDUCING CONGESTION REGION IN LAYOUT AREA OF IC

  • US 20160203254A1
  • Filed: 06/18/2015
  • Published: 07/14/2016
  • Est. Priority Date: 01/08/2015
  • Status: Active Grant
First Claim
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1. A method for reducing congestion regions in a layout of an integrated circuit, comprising:

  • obtaining a placement of the integrated circuit, wherein the placement comprises a first signal path between a first macro module and a second macro module, and the first signal path passes through a routing area of the placement for transmitting a specific signal;

    identifying a congestion region of the routing area, wherein the first signal path comprises at least one cell or at least one routing path in the congestion region;

    obtaining a cost evaluation for each candidate position of the routing area by moving the cell or the routing path out of the congestion region; and

    moving the cell or the macro module corresponding to the routing path to the candidate position having a minimum cost evaluation among the cost evaluations, and simultaneously updating the placement and the routing paths according to the cell or the macro module moved to the candidate position having the minimum cost evaluation.

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