MEMORY SYSTEM AND INFORMATION PROCESSING SYSTEM

• US 20160203342A1
• Filed: 08/25/2015
• Published: 07/14/2016
• Est. Priority Date: 01/09/2015
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: MATSUO, Kiyotaka
• Granted Patent: US 9,904,807 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2221/2107 File encryption
• CPC Class Codes: G06F 3/0623 in relation to content
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A memory system includes a controller configured to write data to a nonvolatile memory. The controller includes a buffer unit configured to hold write data including a plurality of pieces of unit data, a sequencer configured to receive the write data from the buffer unit and individually output the plurality of pieces of unit data sequentially, and a plurality of cores, each being configured to encrypt at least one of the pieces of unit data output from the sequencer. The buffer is further configured to output the plurality of pieces of unit data sequentially to the sequencer, such that a last piece of unit data is output consecutively after a preceding piece of unit data is output.

Claims

1. A memory system comprising a controller configured to write data to a nonvolatile memory, wherein the controller includes:

a buffer unit configured to hold write data including a plurality of pieces of unit data;

a sequencer configured to receive the write data from the buffer unit and individually output the plurality of pieces of unit data sequentially; and

a plurality of cores, each being configured to encrypt at least one of the pieces of unit data output from the sequencer, wherein

the buffer is further configured to output the plurality of pieces of unit data sequentially to the sequencer, such that a last piece of unit data is output consecutively after a preceding piece of unit data is output.

2. The memory system according to claim 1, wherein

one of the cores encrypts both the last piece of unit data and the preceding piece of unit data.

3. The memory system according to claim 1, wherein

the buffer unit is further configured to output a header to the sequencer prior to outputting the write data.

4. The memory system according to claim 1, further comprising:

a checker configured to receive from the sequencer a request to search a key identification code; and

a search unit configured to search for an encryption key corresponding to the key identification code.

5. The memory system according to claim 4, wherein

the search unit stores correspondence between the key identification code and the encryption key.

6. The memory system according to claim 4, wherein each of the cores includes

a key expansion unit configured to expand the encryption key, and

a core encryption unit configured to encrypt an initialization vector using the expanded encryption key, and the piece of unit data using the encrypted initialization vector.

7. The memory system according to claim 4, further comprising:

a second core including a key expansion unit configured to expand the encryption key, and a core encryption unit configured to encrypt an initialization vector using the expanded encryption key, and configured to output the encrypted initialization vector to each of the cores.

8. The memory system according to claim 7, wherein

each of the cores encrypts the piece of unit data using the encrypted initialization vector output from the second core.

9. The memory system according to claim 7, wherein

the checker is further configured to receive from the sequencer a second request to search a second key identification code for second write data output from the buffer unit,

the search unit is further configured to search for a second encryption key corresponding to the second key identification code, and

the key expansion unit is further configured to expand the second encryption key while one of the cores encrypts a piece of unit data.

10. The memory system according to claim 1, wherein

the sequencer is further configured to receive second write data from the buffer unit after receiving the write data, and includes a counter configured to count the number of pieces of unit data in the write data and calculate a sum of the number and the number of pieces of unit data in the second write data.

11. The memory system according to claim 1, wherein

the sequencer is further configured to receive from the buffer unit second write data that includes a plurality of pieces of unit data, after receiving the write data, and output the plurality of pieces of unit data in the second write data sequentially to the plurality of cores, and

a first piece of unit data in the second write data is output to one of the cores that is configured to receive a piece of unit data that is immediately subsequent to a piece of unit data received by another one of the cores that receives the last piece of unit data.

12. The memory system according to claim 1, further comprising:

a second sequencer configured to receive the encrypted pieces of unit data from the plurality of cores; and

a writing unit configured to write the encrypted pieces of unit data in the nonvolatile memory.

13. An information processing system, comprising:

a host configured to transmit write data including a plurality of pieces of unit data;

a nonvolatile memory; and

a controller configured to receive the write data from the host and write the write data to the nonvolatile memory, wherein

the controller includes;

a buffer unit configured to hold the write data;

a sequencer configured to receive the write data from the buffer unit and individually output the plurality of pieces of unit data sequentially; and

a plurality of cores, each being configured to encrypt at least one of the pieces of unit data output from the sequencer, and

the buffer is further configured to output the plurality of pieces of unit data sequentially to the sequencer, such that a last piece of unit data is output consecutively after a preceding piece of unit data is output.

14. The information processing system according to claim 13, wherein

one of the cores encrypts both the last piece of unit data and the preceding piece of unit data.

15. The information processing system according to claim 13, wherein

the buffer unit is further configured to output a header to the sequencer prior to outputting the write data.

16. The information processing system according to claim 13, wherein the controller further includes:

a checker configured to receive from the sequencer a request to search a key identification code; and

a search unit configured to search for an encryption key corresponding to the key identification code.

17. The information processing system according to claim 16, wherein the controller further includes:

a second core including a key expansion unit configured to expand the encryption key, and a core encryption unit configured to encrypt an initialization vector using the expanded encryption key, and configured to output the encrypted initialization vector to each of the cores.

18. The information processing system according to claim 17, wherein

the checker is further configured to receive from the sequencer a second request to search a second key identification code for second write data output from the buffer unit,

the search unit is further configured to search for a second encryption key corresponding to the second key identification code, and

the key expansion unit is further configured to expand the second encryption key while one of the cores encrypts a piece of unit data.

19. The information processing system according to claim 13, wherein

the sequencer is further configured to receive second write data from the buffer unit after receiving the write data, and includes a counter configured to count the number of pieces of unit data in the write data and calculate a sum of the number and the number of pieces of unit data in the second write data.

20. The information processing system according to claim 13, wherein

the sequencer is further configured to receive from the buffer unit second write data that includes a plurality of pieces of unit data, after receiving the write data, and output the plurality of pieces of unit data in the second write data sequentially to the plurality of cores, and

a first piece of unit data in the second write data is output to one of the cores that is configured to receive a piece of unit data that is immediately subsequent to a piece of unit data received by another one of the cores that receives the last piece of unit data.