TECHNIQUES TO AVOID OR LIMIT IMPLANT PUNCH THROUGH IN SPLIT GATE FLASH MEMORY DEVICES

• US 20160204118A1
• Filed: 01/14/2015
• Published: 07/14/2016
• Est. Priority Date: 01/14/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Yung-Chang, Wu, Chang-Ming, Liu, Shih-Chang, Chen, Sheng-Chieh
• Granted Patent: US 9,716,097 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/32137 of silicon-containing layers
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/43 comprising only one type of peripheral transistor

Abstract

Some embodiments of the present disclosure relate to a flash memory device. The flash memory device includes first and second individual source/drain (S/D) regions spaced apart within a semiconductor substrate. A common S/D region is arranged laterally between the first and second individual S/D regions, and is separated from the first individual S/D region by a first channel region and is separated from the second individual S/D region by a second channel region. An erase gate is arranged over the common S/D. A floating gate is disposed over the first channel region and is arranged to a first side of the erase gate. A control gate is disposed over the floating gate. A wordline is disposed over the first channel region and is spaced apart from the erase gate by the floating gate and the control gate. An upper surface of the wordline is a concave surface.

Claims

1. A flash memory device comprising:

first and second individual source/drain (S/D) regions spaced apart within a semiconductor substrate;

a common S/D region arranged laterally between the first and second individual S/D regions, and being separated from the first individual S/D region by a first channel region and being separated from the second individual S/D region by a second channel region;

an erase gate arranged over the common S/D;

a floating gate disposed over the first channel region and to a first side of the erase gate, and a control gate disposed over the floating gate; and

a wordline disposed over the first channel region and spaced apart from the erase gate by the floating gate and the control gate, wherein an upper surface of the wordline is a concave surface.

2. The flash memory device of claim 1, wherein a bottom region of the concave surface is spaced laterally apart from an outer sidewall of the wordline by a first distance and is spaced laterally apart from an inner sidewall of the wordline by a second distance, the first distance being different from the second distance.

3. The flash memory device of claim 1, wherein an outermost side of the concave surface has a first height, and an innermost side of the concave surface, which is opposite the outermost side and which is adjacent to the control gate, has a second height that is greater than the first height.

4. The flash memory device according to claim 1, further comprising:

a composite spacer including an inner layer and an outer layer;

wherein the inner layer covers an upper region of an outer sidewall of the wordline but leaves a lower region of the outer sidewall of the wordline un-covered; and

wherein the outer layer extends along an outer sidewall of the inner layer and extends downward along the un-covered lower region of the outer sidewall of the wordline.

5. The flash memory device of claim 4, wherein the composite spacer further includes an outermost layer extending along an outer sidewall of the outer layer, wherein the inner layer is made of a nitride material, the outer layer is made of oxide, and the outermost layer is made of the nitride material.

6. A flash memory device comprising a pair of split gate memory cells, the pair of split gate memory cells comprising:

first and second individual source/drain (S/D) regions spaced apart within a semiconductor substrate;

a common S/D region arranged laterally between the first and second individual S/D regions, and being separated from the first individual S/D region by a first channel region and being separated from the second individual S/D region by a second channel region;

an erase gate arranged over the common S/D;

a first floating gate disposed over the first channel region and to a first side of the erase gate, and a first control gate disposed over the first floating gate;

a first wordline disposed over the first channel region and spaced apart from the erase gate by the first floating gate, the first wordline having an outer wordline sidewall facing the first individual S/D region; and

a first composite spacer including a first inner layer and a first outer layer, the first inner layer covering an upper region of the outer wordline sidewall but leaving a lower region of the outer wordline sidewall un-covered, and the first outer layer extending along an outer sidewall of the first inner layer and extending downward along the un-covered lower region of the outer wordline sidewall.

7. The flash memory device of claim 6, wherein the first composite spacer further includes a first outermost layer extending along an outer sidewall of the first outer layer.

8. The flash memory device of claim 7, wherein:

the first inner layer is made of SiN and has a lateral thickness ranging between 20 angstroms and 100 angstroms;

the first outer layer is made of oxide and has a lateral thickness ranging between 100 angstroms and 200 angstroms; and

the first outermost layer is made of SiN and has a lateral thickness ranging between 200 angstroms and 300 angstroms.

9. The flash memory device of claim 6, wherein a top surface of the first wordline is a concave surface.

10. The flash memory device of claim 9, wherein a bottom region of the concave surface is spaced laterally apart from the outer wordline sidewall by a first distance and is spaced laterally apart from an inner wordline sidewall of the first wordline by a second distance, the first distance being smaller than the second distance.

11. The flash memory device of claim 9, wherein an outermost side of the concave surface, which is adjacent to the outer wordline sidewall, has a first height, and an innermost side of the concave surface, which is adjacent to the control gate, has a second height that is greater than the first height.

12. The flash memory device of claim 6, further comprising:

a hard mask over the control gate, wherein the first inner layer has an uppermost surface having a height that ranges between 50% and 95% of the height of the upper surface of the hard mask, as measured from an upper surface of the semiconductor substrate.

13. The flash memory device of claim 6, further comprising:

a second floating gate disposed over the second channel region and to a second side of the erase gate, and a second control gate disposed over the second floating gate;

a second wordline disposed over the second channel region and spaced apart from the erase gate by the second floating gate and the second control gate, the second wordline having an outer wordline sidewall facing the second individual S/D region; and

a second composite spacer including a second inner layer and a second outer layer, the second inner layer covering an upper region of the outer wordline sidewall but leaving a lower region of the outer wordline sidewall un-covered, and the second outer layer extending along an outer sidewall of the second inner layer and extending downward along the un-covered lower region of the outer wordline sidewall.

14. The flash memory device of claim 13, further comprising composite spacers over the erase gate.

15. The flash memory device of claim 6, further comprising:

a logic gate with a top surface approximately even with a word line ledge;

an interlayer dielectric (ILD) layer arranged over the erase gate and the word line; and

a contact extending through the ILD layer to one of the erase gate and the word line.

16. The flash memory device of claim 6, further including:

silicide pads arranged over the word line and the erase gate.

17. A method for manufacturing an embedded flash memory device, said method comprising:

forming a pair of floating gate transistor gate stacks over a memory region of a semiconductor substrate;

forming a polysilicon layer, a protective layer, and hard mask layer, in that order, over the semiconductor substrate and the gate stacks;

forming a first mask covering the memory region and having openings over a logic region of the semiconductor substrate, and patterning the polysilicon layer, the protective layer, and the hard mask with the first mask in place;

forming a second mask covering the logic region;

removing exposed portions of the hard mask and exposed portions of the protective layer to form protective spacers over the memory region; and

with the second mask and protective spacers in place, etching back portions of the polysilicon layer to form wordlines and erase gates over the memory region.

18. The method of claim 17, wherein an upper surface of the wordline is a concave surface after being etched back.

19. The method of claim 17, further comprising:

removing the second mask;

removing the hard mask and the protective layer from over the logic region; and

forming outer and outermost layers about the protective spacers to form composite spacers on outermost sidewalls of the wordlines.

20. The method of claim 18, further comprising:

with the composite spacers and wordlines in place, performing ion implantation to form individual source/drain regions in substrate.