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TECHNIQUES TO AVOID OR LIMIT IMPLANT PUNCH THROUGH IN SPLIT GATE FLASH MEMORY DEVICES

  • US 20160204118A1
  • Filed: 01/14/2015
  • Published: 07/14/2016
  • Est. Priority Date: 01/14/2015
  • Status: Active Grant
First Claim
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1. A flash memory device comprising:

  • first and second individual source/drain (S/D) regions spaced apart within a semiconductor substrate;

    a common S/D region arranged laterally between the first and second individual S/D regions, and being separated from the first individual S/D region by a first channel region and being separated from the second individual S/D region by a second channel region;

    an erase gate arranged over the common S/D;

    a floating gate disposed over the first channel region and to a first side of the erase gate, and a control gate disposed over the floating gate; and

    a wordline disposed over the first channel region and spaced apart from the erase gate by the floating gate and the control gate, wherein an upper surface of the wordline is a concave surface.

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