TECHNIQUES TO AVOID OR LIMIT IMPLANT PUNCH THROUGH IN SPLIT GATE FLASH MEMORY DEVICES
First Claim
1. A flash memory device comprising:
- first and second individual source/drain (S/D) regions spaced apart within a semiconductor substrate;
a common S/D region arranged laterally between the first and second individual S/D regions, and being separated from the first individual S/D region by a first channel region and being separated from the second individual S/D region by a second channel region;
an erase gate arranged over the common S/D;
a floating gate disposed over the first channel region and to a first side of the erase gate, and a control gate disposed over the floating gate; and
a wordline disposed over the first channel region and spaced apart from the erase gate by the floating gate and the control gate, wherein an upper surface of the wordline is a concave surface.
1 Assignment
0 Petitions
Accused Products
Abstract
Some embodiments of the present disclosure relate to a flash memory device. The flash memory device includes first and second individual source/drain (S/D) regions spaced apart within a semiconductor substrate. A common S/D region is arranged laterally between the first and second individual S/D regions, and is separated from the first individual S/D region by a first channel region and is separated from the second individual S/D region by a second channel region. An erase gate is arranged over the common S/D. A floating gate is disposed over the first channel region and is arranged to a first side of the erase gate. A control gate is disposed over the floating gate. A wordline is disposed over the first channel region and is spaced apart from the erase gate by the floating gate and the control gate. An upper surface of the wordline is a concave surface.
-
Citations
20 Claims
-
1. A flash memory device comprising:
-
first and second individual source/drain (S/D) regions spaced apart within a semiconductor substrate; a common S/D region arranged laterally between the first and second individual S/D regions, and being separated from the first individual S/D region by a first channel region and being separated from the second individual S/D region by a second channel region; an erase gate arranged over the common S/D; a floating gate disposed over the first channel region and to a first side of the erase gate, and a control gate disposed over the floating gate; and a wordline disposed over the first channel region and spaced apart from the erase gate by the floating gate and the control gate, wherein an upper surface of the wordline is a concave surface. - View Dependent Claims (2, 3, 4, 5)
-
-
6. A flash memory device comprising a pair of split gate memory cells, the pair of split gate memory cells comprising:
-
first and second individual source/drain (S/D) regions spaced apart within a semiconductor substrate; a common S/D region arranged laterally between the first and second individual S/D regions, and being separated from the first individual S/D region by a first channel region and being separated from the second individual S/D region by a second channel region; an erase gate arranged over the common S/D; a first floating gate disposed over the first channel region and to a first side of the erase gate, and a first control gate disposed over the first floating gate; a first wordline disposed over the first channel region and spaced apart from the erase gate by the first floating gate, the first wordline having an outer wordline sidewall facing the first individual S/D region; and a first composite spacer including a first inner layer and a first outer layer, the first inner layer covering an upper region of the outer wordline sidewall but leaving a lower region of the outer wordline sidewall un-covered, and the first outer layer extending along an outer sidewall of the first inner layer and extending downward along the un-covered lower region of the outer wordline sidewall. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
-
-
17. A method for manufacturing an embedded flash memory device, said method comprising:
-
forming a pair of floating gate transistor gate stacks over a memory region of a semiconductor substrate; forming a polysilicon layer, a protective layer, and hard mask layer, in that order, over the semiconductor substrate and the gate stacks; forming a first mask covering the memory region and having openings over a logic region of the semiconductor substrate, and patterning the polysilicon layer, the protective layer, and the hard mask with the first mask in place; forming a second mask covering the logic region; removing exposed portions of the hard mask and exposed portions of the protective layer to form protective spacers over the memory region; and with the second mask and protective spacers in place, etching back portions of the polysilicon layer to form wordlines and erase gates over the memory region. - View Dependent Claims (18, 19, 20)
-
Specification