METHOD FOR PREVENTING COPPER CONTAMINATION IN METAL-INSULATOR-METAL (MIM) CAPACITORS

• US 20160204190A1
• Filed: 01/08/2015
• Published: 07/14/2016
• Est. Priority Date: 01/08/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chu, Ching-Sheng, Hsu, Chern-Yow, Liu, Shih-Chang
• Granted Patent: US 9,793,339 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53266 Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 28/75 comprising two or more layers, e.g. comprising a barrier layer and a metal layer
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The present disclosure relates to a MIM capacitor that includes a composite capacitor top metal (CTM) electrode and a composite capacitor bottom metal (CBM) electrode. The composite CBM electrode includes a first diffusion barrier layer overlying a first metal layer, and the composite CTM electrode includes a second diffusion barrier layer overlying a second metal layer. A dielectric layer is arranged over the composite CBM electrode, underlying the composite CTM electrode. The first and second diffusion barrier layers protect the first and second metal layers from metal that diffuses or moves from a metal line underlying the MIM capacitor to the composite CTM and CBM electrodes during manufacture. A method of manufacturing the MIM capacitor is also provided.

Claims

1. A semiconductor structure comprising a metal-insulator-metal (MIM) capacitor, the MIM capacitor including:

a composite capacitor bottom metal (CBM) electrode including a first diffusion barrier layer overlying a first metal layer;

a dielectric layer arranged over the composite CBM electrode;

a composite capacitor top metal (CTM) electrode arranged over the dielectric layer and including a second diffusion barrier layer overlying a second metal layer;

a bottom electrode hard mask covering the composite CTM electrode and the dielectric layer, wherein the bottom electrode hard mask has a same footprint as the composite CBM electrode; and

a via extending to the first or second diffusion barrier layer.

2. The semiconductor structure of claim 1,

where the via extends into the first or second diffusion barrier layer to a point within the first or second diffusion barrier layer that is spaced from the first and second metal layers, and wherein a bottom of the first or second diffusion barrier layer is flat from a first end of the first or second diffusion barrier layer to a second end of the first or second diffusion barrier layer that is opposite the first end.

3. The semiconductor structure of claim 2, wherein the via extends into the first diffusion barrier layer, and wherein the MIM capacitor further includes:

a second via extending into the second diffusion barrier layer to a point within the second diffusion barrier layer that is spaced from the first and second metal layers.

4. The semiconductor structure of claim 1, further including:

a back end of line (BEOL) stack including a lower metallization layer and an upper metallization layer respectively arranged under and over the MIM capacitor, and further comprising a second via extending from the upper metallization layer to the lower metallization layer; and

an interlayer dielectric (ILD) layer arranged vertically between the composite CBM electrode and the lower metallization layer and configured to electrically isolate the composite CBM electrode from the lower metallization layer.

5. The semiconductor structure of claim 1, wherein the first and second metal layers include titanium (Ti) or titanium nitride (TiN), and wherein the first and second diffusion barrier layers include tantalum nitride (TaN) or niobium nitride (NbN).

6. The semiconductor structure of claim 1, wherein the first and second diffusion barrier layers are amorphous metals.

8. The semiconductor structure of claim 1, wherein the MIM capacitor further includes:

a top electrode hard mask arranged over the composite CTM electrode, wherein the bottom electrode hard mask conformally lines upper surfaces of the dielectric layer and the top electrode hard mask, and wherein the bottom electrode hard mask further conformally lines sidewall surfaces of the top electrode hard mask and the composite CTM electrode.

9. The semiconductor structure of claim 1, further including:

an interlayer dielectric (ILD) layer surrounding the MIM capacitor;

a via opening extending through the ILD layer into the first or second diffusion barrier layer to a point within the first or second diffusion barrier layer that is spaced from the first and second metal layers; and

a third diffusion barrier layer lining the via opening;

wherein the via fills the via opening over the third diffusion barrier layer.

21. The semiconductor structure of claim 4, wherein the first metal layer directly abuts the ILD layer, wherein the second metal layer directly abuts the dielectric layer, and wherein the dielectric layer directly abuts the first diffusion barrier layer.

7. (canceled)

10. A method of forming a semiconductor structure, said method comprising:

forming an interlayer dielectric (ILD) layer covering a first metallization layer of a back end of line (BEOL) stack;

forming a metal-insulator-metal (MIM) capacitor confined to over the ILD layer, the MIM capacitor including a composite capacitor top metal (CTM) electrode overlying a composite capacitor bottom metal (CBM) electrode, and the composite CBM and CTM electrodes including corresponding metal layers and corresponding diffusion barrier layers overlying the corresponding metal layers;

forming a second metallization layer of the BEOL stack over the MIM capacitor;

forming a first via extending from the second metallization layer into one of the diffusion barrier layers to a point within the one of the diffusion barrier layers that is spaced from the metal layers; and

forming a second via laterally spaced from the MIM capacitor and extending from the first metallization layer to the second metallization layer.

11. The method of claim 10, further including:

forming a second via extending from the second metallization layer into another one of the diffusion barrier layers to a point within the other one of the diffusion barrier layers that is spaced from the metal layers.

12. The method of claim 10, further including:

forming a second interlayer dielectric (ILD) layer over the MIM capacitor;

performing an etch into the second ILD layer to form via openings and trenches, the via openings respectively extending to the MIM capacitor and the first metallization layer, and the trenches defining a pattern of the second metallization layer;

forming a conductive layer over the second ILD layer and filling the trenches and the via openings to form vias; and

performing a planarization into the conductive layer to form the second metallization layer.

13. The method of claim 12, further including:

forming an additional diffusion barrier layer lining the trenches and the via openings before forming the conductive layer.

14. The method of claim 10, further including forming the MIM capacitor by at least:

forming a composite CBM layer;

forming a dielectric layer over the composite CBM layer;

forming a composite CTM layer over the dielectric layer;

forming a top electrode hard mask over the composite CTM layer to mask a CTM electrode region of the composite CTM layer;

performing a first etch through regions of the composite CTM layer unmasked by the top electrode hard mask to form the composite CTM electrode;

forming a bottom electrode hard mask lining upper surfaces of the dielectric layer and the to electrode hard mask, and further lining sidewall surfaces of the composite CTM electrode and the top electrode hard mask, to mask a CBM electrode region of the composite CBM layer; and

performing a second etch through regions of the composite CBM layer unmasked by the bottom electrode hard mask to form the composite CBM electrode.

15. The method of claim 14, further including:

forming the composite CBM layer by at least;

forming a first metal layer directly on the ILD layer; and

forming a first diffusion barrier layer directly on the first metal layer;

forming the dielectric layer directly on the first diffusion barrier layer; and

forming the composite CTM layer by at least;

forming a second metal layer directly on the dielectric layer; and

forming a second diffusion barrier layer directly on the second metal layer.

16. The method of claim 10, further including:

forming the diffusion barrier layers with tantalum nitride (TaN) or niobium nitride (NbN).

18. The method of claim 10, further including:

forming the composite CTM electrode with a smaller footprint than the composite CBM electrode.

17. (canceled)

19. An integrated circuit (IC) comprising:

a metal-insulator-metal (MIM) capacitor including a bottom electrode, a top electrode, and a dielectric layer arranged between the top and bottom electrodes, wherein the top and bottom electrodes include corresponding metal layers and corresponding diffusion barrier layers overlying the corresponding metal layers;

a back end of line (BEOL) stack including a lower metallization layer and an upper metallization layer respectively arranged under and over the MIM capacitor;

a first via and a second via extending from the upper metallization layer respectively into the diffusion barrier layers to points within the diffusion barrier layers that are spaced from the metal layers;

a third via laterally spaced from the MIM capacitor and extending from the upper metallization layer to the lower metallization layer; and

an interlayer dielectric (ILD) layer arranged between the bottom electrode and the lower metallization layer, wherein the MIM capacitor is confined over the ILD layer.

20. The IC of claim 19, wherein the diffusion barrier layer includes tantalum (Ta) or niobium (Nb).

22. The IC of claim 19, further comprising:

a top electrode hard mask arranged over the top electrode; and

a bottom electrode hard mask conformally lining upper surfaces of the top electrode hard mask and the dielectric layer, and further conformally lining sidewall surfaces of the top electrode hard mask and the top electrode.