INSULATED GATE POWER DEVICE USING A MOSFET FOR TURNING OFF

• US 20160204239A1
• Filed: 01/12/2016
• Published: 07/14/2016
• Est. Priority Date: 01/13/2015
• Status: Active Grant

• Current Assignee: Pakal Technologies, Inc.
• Original Assignee: Pakal Technologies, LLC
• Inventors: Rodov, Vladimir, Blanchard, Richard A., Akiyama, Hidenori, Tworzydlo, Woytek
• Granted Patent: US 9,806,181 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/66371 structurally associated with another device, e.g. built-in diode making integrated circuits H01L21/82
• CPC Class Codes: H01L 29/7404 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7455 produced by an insulated gate structure
• CPC Class Codes: H01L 29/749 with turn-on by field effect

Abstract

An insulated gate turn-off (IGTO) device has a PNPN layered structure so that vertical NPN and PNP transistors are formed. Trench gates are formed extending into the intermediate P-layer. The device is formed of an array of cells. A P-channel MOSFET, having a trenched gate, is formed in some of the cells. The control terminal of the IGTO device is connected to the insulated gates of all cells, including to the gate of the P-channel MOSFET, and to the intermediate P-layer. To turn the device on, a positive voltage is applied to the control terminal to turn on the NPN transistor by forward biasing its base-emitter. To turn off the IGTO device, a negative voltage is applied to the control terminal to turn on the P-channel MOSFET to short the NPN base to its emitter.

Claims

1. An insulated gate turn-off (IGTO) device comprising:

a first semiconductor layer of a first conductivity type;

a second semiconductor layer of a second conductivity type overlying the first semiconductor layer;

a third semiconductor layer of the first conductivity type overlying at least a portion of the second semiconductor layer;

an array of cells comprising a plurality of insulated gates within trenches formed at least within the third semiconductor layer;

at least some of the cells being a first type of cell comprising;

a first insulated gate formed within a trench terminating within the third semiconductor layer;

a first semiconductor region of the second conductivity type over the third semiconductor layer and adjacent to the first insulated gate;

a second semiconductor region of the first conductivity type over the first semiconductor region and adjacent to the first insulated gate region;

wherein the second semiconductor region, the first semiconductor region, the third semiconductor layer, and the first insulated gate form a first MOSFET;

wherein the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer form a first emitter, first base, and first collector, respectively, of a vertical first bipolar transistor of a first type;

wherein the first semiconductor region, the third semiconductor layer, and the second semiconductor layer form a second emitter, second base, and second collector, respectively, of a vertical second bipolar transistor of a second type;

a first electrode electrically coupled to the first semiconductor layer;

a second electrode electrically coupled to the first semiconductor region and the second semiconductor region and shorting the first semiconductor region to the second semiconductor region; and

wherein a first voltage of a first polarity, relative to a second voltage on the second electrode, applied to the first insulated gate turns on the first MOSFET, which turns off the second bipolar transistor by forming a conductive channel between the second emitter and the second base of the second bipolar transistor, and wherein turning off the second bipolar transistor turns off the IGTO device.

2. The device of claim 1 wherein the first conductivity type is a p-type, and the second conductivity type is an n-type.

3. The device of claim 1 wherein the first conductivity type is an n-type, and the second conductivity type is a p-type.

4. The device of claim 1 wherein the first semiconductor layer is a starting substrate.

5. The device of claim 1 wherein the third semiconductor layer is formed as a well with implanted dopants.

6. The device of claim 1 wherein the first electrode is an anode electrode and the second electrode is a cathode electrode.

7. The device of claim 1 further comprising a control terminal electrically coupled to the first insulated gate, wherein the control terminal is also electrically coupled to the third semiconductor layer, such that a third voltage, having a polarity opposite to that of the first voltage, applied to the control terminal forward biases the second base and second emitter of the second bipolar transistor to turn it on, which turns on the IGTO device.

8. The device of claim 7 further comprising a diode between the control terminal and the third semiconductor layer.

9. The device of claim 1 wherein the first type of cell is distributed among the array of cells.

10. The device of claim 9 wherein the first type of cell forms fewer than half of all the cells in the array of cells.

11. The device of claim 1 further comprising:

a second insulated gate that extends through the third semiconductor layer and into the second semiconductor layer, the second insulated gate being electrically coupled to the first insulated gate;

a third semiconductor region of the second conductivity type adjacent the second insulated gate,

wherein the third semiconductor region, the third semiconductor layer, and the second semiconductor layer form a second MOSFET; and

wherein a third voltage, having a polarity opposite to that of the first voltage, applied to the second insulated gate turns on the second MOSFET to conduct a current between the third semiconductor region and the second semiconductor layer to inject carriers into the second semiconductor layer to initiate turn on of the IGTO device.

12. The device of claim 11 wherein the second MOSFET is an N-channel MOSFET.

13. A method performed by an insulated gate turn-off (IGTO) device, the device comprising:

a first semiconductor layer of a first conductivity type;

a second semiconductor layer of a second conductivity type overlying the first semiconductor layer;

a third semiconductor layer of the first conductivity type overlying at least a portion of the second semiconductor layer;

an array of cells comprising a plurality of insulated gates within trenches formed at least within the third semiconductor layer;

at least some of the cells being a first type of cell comprising;

a first insulated gate formed within a trench terminating within the third semiconductor layer;

a first semiconductor region of the second conductivity type over the third semiconductor layer and adjacent to the first insulated gate;

a second semiconductor region of the first conductivity type over the first semiconductor region and adjacent to the first insulated gate region;

wherein the second semiconductor region, the first semiconductor region, the third semiconductor layer, and the first insulated gate forms a first MOSFET;

wherein the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer form a first emitter, first base, and first collector, respectively, of a vertical first bipolar transistor of a first type;

wherein the first semiconductor region, the third semiconductor layer, and the second semiconductor layer form a second emitter, second base, and second collector, respectively, of a vertical second bipolar transistor of a second type;

a first electrode electrically coupled to the first semiconductor layer;

a second electrode electrically coupled to the first semiconductor region and the second semiconductor region and shorting the first semiconductor region to the second semiconductor region;

the method comprising;

applying a first voltage of a first polarity, relative to a second voltage on the second electrode, to the first insulated gate to turn on the first MOSFET, which turns off the second bipolar transistor by forming a conductive channel between the second emitter and the second base of the second bipolar transistor, and wherein turning off the second bipolar transistor turns off the IGTO device.

14. The method of claim 13 wherein the device further comprises a control terminal electrically coupled to the first insulated gate, wherein the control terminal is also electrically coupled to the third semiconductor layer,

wherein the method further comprises applying a third voltage, having a polarity opposite to that of the first voltage, to the control terminal to forward bias the second base and second emitter of the second bipolar transistor to turn it on, which turns on the IGTO device.

15. The method of claim 13 wherein the device further comprises:

a second insulated gate that extends through the third semiconductor layer and into the second semiconductor layer, the second insulated gate being electrically coupled to the first insulated gate;

a third semiconductor region of the second conductivity type adjacent the second insulated gate,

wherein the third semiconductor region, the third semiconductor layer, and the second semiconductor layer form a second MOSFET;

wherein the method further comprises applying a third voltage, having a polarity opposite to that of the first voltage, to the second insulated gate to turn on the second MOSFET to conduct a current between the third semiconductor region and the second semiconductor layer to inject carriers into the second semiconductor layer to initiate turn on of the IGTO device.

16. The method of claim 15 wherein the first MOSFET is a P-channel MOSFET and the second MOSFET is an N-channel MOSFET.

17. The method of claim 13 wherein the first conductivity type is a p-type, and the second conductivity type is an n-type.

18. The method of claim 13 wherein the first conductivity type is an n-type, and the second conductivity type is a p-type.

19. The method of claim 13 wherein the first semiconductor layer is a starting substrate.

20. The method of claim 13 wherein the third semiconductor layer is formed as a well with implanted dopants.