IMPROVED CLADDING LAYER EPITAXY VIA TEMPLATE ENGINEERING FOR HETEROGENEOUS INTEGRATION ON SILICON

• US 20160204263A1
• Filed: 09/27/2013
• Published: 07/14/2016
• Est. Priority Date: 09/27/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: MUKHERJEE, Niloy, RADOSAVLJEVIC, Marko, KAVALIEROS, Jack T., PILLARISETTY, Ravi, GOEL, Niti, LE, Van H., DEWEY, Gilbert, CHU-KUNG, Benjamin
• Granted Patent: US 10,693,008 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02428 Structure
• CPC Class Codes: H01L 21/02538 Group 13/15 materials
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/0688 characterised by the particular shape of a junction between semiconductor regions
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66431 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT with an active layer made of a group 13/15 material H01L29/66462
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7853 the body having a non-rectangular crossection
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

An apparatus including a semiconductor body including a channel region and junction regions disposed on opposite sides of the channel region, the semiconductor body including a first material including a first band gap; and a plurality of nanowires including a second material including a second band gap different than the first band gap, the plurality of nanowires disposed in separate planes extending through the first material so that the first material surrounds each of the plurality of nanowires; and a gate stack disposed on the channel region. A method including forming a plurality of nanowires in separate planes above a substrate, each of the plurality of nanowires including a material including a first band gap; individually forming a cladding material around each of the plurality of nanowires, the cladding material including a second band gap; coalescing the cladding material; and disposing a gate stack on the cladding material.

Claims

1. A semiconductor apparatus comprising:

a three-dimensional semiconductor body comprising a channel region and junction regions disposed on opposite sides of the channel region, the three-dimensional semiconductor body comprising;

a first material comprising a first band gap; and

a plurality of nanowires comprising a second material comprising a second band gap different than the first band gap, the plurality of nanowires disposed in separate planes extending through the first material so that the first material surrounds each of the plurality of nanowires; and

a gate stack disposed on the channel region, the gate stack comprising a gate electrode disposed on a gate dielectric.

2. The apparatus of claim 1, wherein the band gap of the first material is less than the band gap of the second material.

3. The apparatus of claim 1, wherein the first material comprises a group III and group V compound material.

4. The apparatus of claim 1, wherein the first material is selected from the group consisting of InGaAs/InP, GaAs/AlGaAs and InSb/AlInSb.

5. The apparatus of claim 1, wherein the first material comprises germanium and the second material comprises silicon.

6. The apparatus of claim 1, wherein a cross-sectional shape of the first material is different than a cross-sectional shape of the plurality of nanowires.

7. The apparatus of claim 1, wherein the three-dimensional semiconductor body is disposed on a semiconductor substrate.

8. A semiconductor apparatus comprising:

a fin comprising a plurality of nanowires arranged in a stacked arrangement on a substrate, each nanowire comprising a material having a first band gap and a cladding material comprising a second band gap surrounding each of the plurality of nanowires and coalesced into one body;

a gate stack disposed on a channel region of the fin, the gate stack comprising a gate dielectric and a gate electrode; and

a source region and a drain each defined in the fin on opposite sides of the channel region.

9. The apparatus of claim 8, wherein the band gap of the cladding material is less than the band gap of a material of the nanowires.

10. The apparatus of claim 8, wherein the cladding material comprises a group III and group V compound material.

11. The apparatus of claim 8, wherein the cladding material is selected from the group consisting of InGaAs/InP, GaAs/AlGaAs and InSb/AlInSb.

12. The apparatus of claim 8, wherein the cladding material comprises germanium and a material of the nanowires comprises silicon.

13. The apparatus of claim 8, wherein a cross-sectional shape of the first material is different than a cross-sectional shape of the plurality of nanowires.

14. The apparatus of claim 8, wherein the three-dimensional semiconductor body is disposed on a semiconductor substrate.

15. A method of manufacturing a semiconductor device comprising:

forming a plurality of nanowires in separate planes above a substrate, each of the plurality of nanowires comprising a material comprising a first band gap;

individually forming a cladding material around each of the plurality of nanowires, the cladding material comprising a second band gap;

coalescing the cladding material; and

disposing a gate stack on the cladding material, the gate stack comprising a dielectric material and a gate electrode.

16. The method of claim 15, wherein the band gap of the material of the plurality of nanowires is greater than a band gap of the cladding material.

17. The method of claim 15, wherein the cladding material comprises a group III and group V compound material.

18. The method of claim 15, wherein forming the cladding material comprises epitaxially growing the cladding material.

19. The method of claim 15, wherein the material of the plurality of nanowires comprises silicon and the cladding material comprises germanium.

20. A three-dimensional metal oxide semiconductor field effect transistor formed by the method of claim 15.