APPARATUS AND METHOD FOR FAST PHASE LOCKING FOR DIGITAL PHASE LOCKED LOOP

• US 20160204787A1
• Filed: 09/26/2013
• Published: 07/14/2016
• Est. Priority Date: 09/26/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: LOTFY, Amr M., ABD EL-MEJEED, Mamdouh O., ELZINGA, Mark, PARK, Young Min, RAPETA, Jagannadha R., MUSUNURI, Surya, ABDELSALAM, Mohamed A., KURD, Nasser A., ABDELMONEUM, Mohamed A.
• Granted Patent: US 9,628,094 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G04F 10/005 Time-to-digital converters [TDC] analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60
• CPC Class Codes: H03L 2207/06 Phase locked loops with a controlled oscillator having at least two frequency control terminals
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/0992 comprising a counter or a frequency divider
• CPC Class Codes: H03L 7/103 the additional signal being a digital signal
• CPC Class Codes: H03L 7/105 Resetting the controlled oscillator when its frequency is outside a predetermined limit

Abstract

Described is an integrated circuit (IC) with a phase locked loop with capability of fast locking. The IC comprises: a node to provide a reference clock; a digitally controlled oscillator (DCO) to generate an output clock; a divider coupled to the DCO, the divider to divide the output clock and to generate a feedback clock; and control logic operable to reset the DCO and the divider, and operable to release reset in synchronization with the reference clock. An apparatus for zeroing phase error is provided which comprises a first node to provide a reference clock; a second node to provide a feedback clock; a time-to-digital converter, coupled to the first and second nodes, to measure phase error between the reference and feedback clocks; a digital loop filter; and a control unit to adjust the measured phase error, and to provide the adjusted phase error to the digital loop filter.

Claims

1. An integrated circuit (IC) comprising:

a node to provide a reference clock;

a digitally controlled oscillator (DCO) to generate an output clock;

a divider coupled to the DCO, the divider to divide the output clock and to generate a feedback clock; and

control logic operable to reset or disable the DCO and the divider, and operable to release reset in synchronization with the reference clock.

2. The IC of claim 1, wherein the DCO comprises a plurality of DCO cells and switches, wherein each switch is coupled to an output of a DCO cell of the plurality of DCO cells, and wherein each switch is operable to couple the output of the DCO cell to a known voltage level.

3. The IC of claim 1, wherein the DCO is an LC based DCO which is operable to be enabled to oscillate when reset is released.

4. The IC of claim 1, wherein the control logic is operable to control the switches.

5. The IC of claim 1, wherein the divider is operable to divide the output clock in synchronization with the reference clock when the control logic releases reset.

6. The IC of claim 1 further comprises a digital loop filter (DLF) coupled to provide a digital control word to the DCO.

7. The IC of claim 6, wherein the control logic is operable to adjust filter coefficients of the DLF when the control logic is to reset the divider.

8. The IC of claim 1 further comprises a clock distribution network to receive output clock of the DCO, and wherein the divider to divide a clock received from the clock distribution network.

9. The IC of claim 8, wherein the control logic to reset only the divider when delay of the clock distribution network is substantially greater than one cycle of the output clock.

10. The IC of claim 8, wherein the control logic to reset the divider and the DCO when delay of the clock distribution network is less than one cycle of the output clock.

11. A system comprising:

a memory;

an integrated circuit coupled to the memory, the integrated circuit comprising;

a node to provide a reference clock;

a digitally controlled oscillator (DCO) to generate an output clock;

a divider coupled to the DCO, the divider to divide the output clock and to generate a feedback clock; and

control logic operable to reset or disable the DCO and the divider, and operable to release reset in synchronization with the reference clock; and

a wireless interface for allowing the integrated circuit to communicate with another device.

12. The system of claim 11, wherein the integrated circuit forms part of a digital phase locked loop (DPLL).

13. The system of claim 11 further comprises a display unit.

14. (canceled)

15. (canceled)

16. (canceled)

17. An apparatus comprising:

a first node to provide a reference clock;

a second node to provide a feedback clock;

a time-to-digital converter (TDC), coupled to the first and second nodes, to measure phase error between the reference clock and the feedback clock;

a digital loop filter; and

a control unit to adjust the measured phase error, and to provide the adjusted phase error to the digital loop filter.

18. The apparatus of claim 17, wherein the control unit to adjust the measured phase error by subtracting an initial measured phase error from the measured phase error.

19. The apparatus of claim 18 further comprises a divider which is operable to be reset by the control unit, wherein the TDC to provide the initial measured phase error when the divider is reset.

20. The apparatus of claim 17 further comprises:

a memory;

a processor coupled to the memory; and

a wireless interface for allowing the processor to communicate with another device.

21. The apparatus of claim 20 further comprises a display unit.

22. The apparatus of claim 21, wherein the display unit is a touch screen.

23. The apparatus of claim 20, wherein the processor includes a DPLL.