COMPLEMENTARY METAL OXIDE SEMICONDUCTOR (CMOS) ULTRASONIC TRANSDUCERS AND METHODS FOR FORMING THE SAME

• US 20160207760A1
• Filed: 02/12/2016
• Published: 07/21/2016
• Est. Priority Date: 03/15/2013
• Status: Active Grant

• Current Assignee: BFLY Operations, Inc. (Butterfly Network, Inc.)
• Original Assignee: Butterfly Network, Inc.
• Inventors: Rothberg, Jonathan M., Fife, Keith G., Ralston, Tyler S., Charvat, Gregory L., Sanchez, Nevada J.
• Granted Patent: US 9,499,395 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: B06B 1/02 making use of electrical energy B06B1/18, B06B1/20 take precedence
• CPC Class Codes: B06B 1/0292 Electrostatic transducers, e.g. electret-type
• CPC Class Codes: B81B 7/007 Interconnections between the MEMS and external electrical signals
• CPC Class Codes: B81C 1/00134 comprising flexible or deformable structures manufacture of MEMS devices for specific applications, see relevant places, e.g. gyroscopes G01C19/5719, pressure sensors G01L9/0042, accelerometers G01P15/0802, acoustic transducers or diaphragms therefor H04R31/00
• CPC Class Codes: B81C 1/00158 Diaphragms, membranes manufacture process for semi-permeable inorganic membranes B01D67/0039
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 1/00301 Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
• CPC Class Codes: B81C 2201/0195 the layer being unstructured
• CPC Class Codes: B81C 2203/0735 Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit
• CPC Class Codes: B81C 2203/0771 Stacking the electronic processing unit and the micromechanical structure
• CPC Class Codes: G01N 29/2406 Electrostatic or capacitive probes, e.g. electret or cMUT-probes
• CPC Class Codes: H01L 29/84 controllable by variation of applied mechanical force, e.g. of pressure
• CPC Class Codes: H04R 19/005 using semiconductor materials

Abstract

Complementary metal oxide semiconductor (CMOS) ultrasonic transducers (CUTs) and methods for forming CUTs are described. The CUTs may include monolithically integrated ultrasonic transducers and integrated circuits for operating in connection with the transducers. The CUTs may be used in ultrasound devices such as ultrasound imaging devices and/or high intensity focused ultrasound (HIFU) devices.

Claims

1. An apparatus, comprising:

a semiconductor wafer having a complementary metal oxide semiconductor (CMOS) integrated circuit;

a conductive membrane bonded with the semiconductor wafer to form a bonded structure such that a sealed cavity exists between a bonding surface of the semiconductor wafer and a first side of the conductive membrane, the conductive membrane having a second side distal from the bonding surface of the semiconductor wafer; and

a conductive standoff on the first side of the conductive membrane proximate the bonding surface of the semiconductor wafer such that a surface of the conductive standoff forms an interface between the first side of the conductive membrane and the bonding surface, wherein the conductive standoff connects the conductive membrane to the CMOS integrated circuit, and

wherein the bonded structure lacks an electrode that is on the second side of the conductive membrane and that overlies the cavity.

2. The apparatus of claim 1, wherein the conductive membrane is a doped silicon layer.

3. The apparatus of claim 1, wherein the conductive standoff forms a closed contour surrounding the cavity.

4. The apparatus of claim 1, wherein the conductive standoff is formed of titanium nitride (TiN).

5. The apparatus of claim 1, wherein the conductive standoff is formed of a metal.

6. The apparatus of claim 1, wherein the conductive membrane has a thickness less than thirty microns.

7. A method, comprising:

bonding a transfer wafer to a semiconductor wafer to form a bonded structure with a sealed cavity, the semiconductor wafer having a complementary metal oxide semiconductor (CMOS) integrated circuit; and

removing at least a portion of the transfer wafer to define a conductive membrane from a remaining portion of the transfer wafer, wherein the sealed cavity is between a bonding surface of the semiconductor wafer and a first side of the conductive membrane, the conductive membrane having a second side distal from the bonding surface of the semiconductor wafer;

wherein a conductive standoff is disposed on the first side of the conductive membrane proximate the bonding surface of the semiconductor wafer such that a surface of the conductive standoff forms an interface between the first side of the conductive membrane and the bonding surface, wherein the conductive standoff connects the conductive membrane to the CMOS integrated circuit; and

wherein the bonded structure lacks an electrode that is on the second side of the conductive membrane and that overlies the cavity.

8. The method of claim 7, wherein the conductive membrane is a doped silicon layer.

9. The method of claim 7, wherein the conductive standoff forms a closed contour surrounding the cavity.

10. The method of claim 7, wherein the conductive standoff is formed of titanium nitride (TiN).

11. The method of claim 7, wherein the conductive standoff is formed of a metal.

12. The method of claim 7, wherein the conductive membrane has a thickness less than thirty microns.

13. A method, comprising:

forming a complementary metal oxide semiconductor (CMOS) integrated circuit on a semiconductor wafer;

forming a conductive standoff on the semiconductor wafer;

bonding a transfer wafer having at least one conductive layer to the conductive standoff of the semiconductor wafer, and removing a least a portion of the transfer wafer to form;

a bonded structure having a conductive membrane defined at least in part by the at least one conductive layer; and

a sealed cavity between a bonding surface of the semiconductor wafer and a first side of the conductive membrane, the conductive membrane having a second side distal from the bonding surface of the semiconductor wafer;

wherein the conductive standoff is on the first side of the conductive membrane and wherein a surface of the conductive standoff forms an interface between the first side of the conductive membrane and the bonding surface, wherein the conductive standoff connects the conductive membrane to the CMOS integrated circuit; and

wherein the bonded structure lacks an electrode that is on the second side of the conductive membrane and that overlies the cavity.

14. The method of claim 13, wherein the at least one conductive layer of the transfer wafer comprises doped silicon layer.

15. The method of claim 13, wherein the conductive standoff forms a closed contour surrounding the cavity.

16. The method of claim 13, wherein forming the conductive standoff comprises forming the conductive standoff from titanium nitride (TiN).

17. The method of claim 13, wherein forming the conductive standoff comprises forming the conductive standoff from a metal.

18. The method of claim 13, wherein the conductive membrane has a thickness less than thirty microns.