POWER MANAGEMENT SYNCHRONIZATION MESSAGING SYSTEM

• US 20160209897A1
• Filed: 12/28/2015
• Published: 07/21/2016
• Est. Priority Date: 12/22/2010
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: HENRY, G. GLENN, GASKINS, DARIUS D.
• Granted Patent: US 9,829,945 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/24 Resetting means
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 11/1423 by reconfiguration of paths
• CPC Class Codes: G06F 11/3664 Environments for testing or debugging software
• CPC Class Codes: G06F 13/36 for access to common bus or bus system
• CPC Class Codes: G06F 15/163 Interprocessor communication
• CPC Class Codes: G06F 15/82 data or demand driven
• CPC Class Codes: G06F 9/30076 to perform miscellaneous control operations, e.g. NOP
• CPC Class Codes: G06F 9/30083 Power or thermal control instructions
• CPC Class Codes: G06F 9/44505 Configuring for program initiating, e.g. using registry, configuration files
• CPC Class Codes: G06F 9/5094 where the allocation takes into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A multi-die package for a microprocessor provides a power management synchronization system. The package has a plurality of dies. Each die has a plurality of cores, including a single master core. A plurality of sideband non-system-bus inter-die communication wires communicatively couple the dies to each other for a purpose of synchronizing power management. The master core of each die is configured to use one and only one of the inter-die communication wires to transmit power management synchronization messages to each of the other master cores. The master core of each die is also configured to receive power management synchronization messages from each of the other master cores via one or more inter-die communication wires. The cores use this system of inter-die communication wires to synchronize management of resources that affect both the performance and power consumption of the cores.

Claims

1. A multi-die package for a microprocessor comprising:

a plurality of dies;

each die having a plurality of cores, including a single master core; and

a plurality of sideband non-system-bus inter-die communication wires communicatively coupling the dies to each other for a purpose of synchronizing power management;

wherein the master core of each die is configured to use one and only one of the inter-die communication wires to transmit power management synchronization messages to each of the other master cores;

wherein the master core of each die is configured to receive power management synchronization messages from each of the other master cores via one or more inter-die communication wires.

2. The multi-die package of claim 1, wherein each die provides a single output pad and a plurality of input pads for connecting to the inter-die communication wires.

3. The multi-die package of claim 1, wherein each die provides at least two input pads for connecting to the inter-die communication wires, enabling the dies, after manufacture, to be configured in both a two-die multi-core microprocessor and an X-die multi-core microprocessor, where X is greater than or equal to three.

4. The multi-die package of claim 1, further comprising a shift register at an end of each inter-die communication wire that is configured to accumulate a serial stream of bits composing a power management synchronization message.

5. The multi-die package of claim 1, wherein the power management synchronization messages include a requested ratio of a bus block frequency to a core clock frequency or of a core clock frequency to a bus clock frequency.

6. The multi-die package of claim 1, wherein the power management synchronization messages include a C-state request value.

7. The multi-die package of claim 1, wherein the power management synchronization messages include a P-state request value.

8. The multi-die package of claim 1, wherein the power management synchronization messages include a requested voltage identification (VID) value to indicate to a voltage regulator module.

9. The multi-die package of claim 1, wherein each core includes read and write control and status registers configured for use in receiving and transmitting power management synchronization messages with the other cores.

10. The multi-die package of claim 1, further comprising, for each core, power management logic microcode native to that core, wherein each core is configured to respond to an operating system instruction to transition to a target power management-related state by invoking the power management logic microcode.

11. The multi-die package of claim 1, wherein each core is configured to receive a power management synchronization message as an interrupt, and each core includes microcode that defines an inter-core interrupt handler configured to handle an interrupt caused by a power management synchronization message received from another core.

19. The multi-die package of claim 1, wherein each core is configured to receive a power management synchronization message as an interrupt, and each core includes microcode that defines an inter-core interrupt handler configured to handle an interrupt caused by a power management synchronization message received from another core.

12. A multi-die package for a microprocessor comprising:

a plurality of dies;

each die having a plurality of cores, including a single master core; and

a plurality of sideband non-system-bus inter-die communication channels communicatively coupling the dies to each other to enable them to synchronize management of resources shared by the dies;

wherein each communication channel is a one-way channel with a single transmitting end and one or more receiving ends, the channel being dedicated to enabling a single master core to transmit power management synchronization messages to the other master cores, and the channel coupling the master core on its transmitting end to the one or more other master cores on their receiving ends;

wherein each master core is connected on the transmitting end to a single communication channel and on the receiving end to one or more communication channels;

wherein each master core is configured to transmit power management synchronization messages to the one or more other master cores using the single channel on which it can transmit power management synchronization messages;

wherein each master core is configured to receive power management synchronization messages from the one or more other master cores via the one or more communication channels to which it is connected on the receiving end.

13. The multi-die package of claim 12, wherein the inter-die communication channels comprise inter-die communication wires, and each die provides a single output pad and a plurality of input pads for connecting to the inter-die communication wires.

14. The multi-die package of claim 13, wherein each die provides at least two input pads for connecting to the inter-die communication wires, enabling the dies, after manufacture, to be configured in both a two-die multi-core microprocessor and an X-die multi-core microprocessor, where X is greater than or equal to three.

15. The multi-die package of claim 12, further comprising a shift register at an end of each inter-die communication channel that is configured to accumulate a serial stream of bits composing a power management synchronization message.

16. The multi-die package of claim 12, wherein the power management synchronization messages include one or more of the following:

a requested ratio of a bus block frequency to a core clock frequency or of a core clock frequency to a bus clock frequency;

a C-state request value.

a P-state request value, and

a requested voltage identification (VID) value to indicate to a voltage regulator module.

17. The multi-die package of claim 12, wherein each core includes read and write control and status registers configured for use in receiving and transmitting power management synchronization messages with one or more master cores.

18. The multi-die package of claim 12, further comprising, for each core, power management logic microcode native to that core, wherein each core is configured to respond to an operating system instruction to transition to a target power management-related state by invoking the power management logic microcode.