INFORMATION PROCESSING APPARATUS AND FLASH MEMORY CONTROL METHOD

• US 20160210070A1
• Filed: 01/07/2016
• Published: 07/21/2016
• Est. Priority Date: 01/16/2015
• Status: Abandoned Application

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: KURAFUJI, Takashi, AWATANI, Akira
• Application Number:
  US14/990,668
• Publication Number:
  US 20160210070A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 3/0622 in relation to access
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

An information processing apparatus according to the present invention includes: at least one flash memory including a data storage region that stores data and an erase count storage region that stores erase count data indicating the number of times that the data is erased in the data storage region; and a control circuit that is connected between a processor and the at least one flash memory. The control circuit allows changes of data stored in the data storage region by the processor and suppresses changes of the erase count data stored in the erase count storage region by the processor.

Claims

1. An information processing apparatus comprising:

at least one flash memory comprising a data storage region that stores data and an erase count storage region that stores erase count data indicating the number of times that the data is erased in the data storage region; and

a control circuit that is connected between a processor and the at least one flash memory,

wherein the control circuit allows changes of the data stored in the data storage region by the processor and suppresses changes of the erase count data stored in the erase count storage region by the processor.

2. The information processing apparatus according to claim 1, wherein the control circuit erases data stored in the data storage region after erase count data stored in the erase count storage region is updated.

3. The information processing apparatus according to claim 1, wherein:

the erase count storage region comprises a first erase count storage region and a second erase count storage region that store the erase count data,

the at least one flash memory comprises a region information storage region that stores region information indicating which one of the first erase count storage region and the second erase count storage region is valid, and

the control circuit acquires, when data in the data storage region is erased, the erase count data from one of the first erase count storage region and the second erase count storage region which is indicated as valid by the region information, updates the erase count data that has been acquired to store the erase count data that has been updated in the other erase count storage region, and updates the region information to indicate the other erase count storage region as valid.

4. The information processing apparatus according to claim 3, wherein:

the at least one flash memory comprises a plurality of data storage regions, a plurality of first erase count storage regions, and a plurality of second erase count storage regions, and

the control circuit acquires, for the erase count storage region corresponding to the data storage region in which the data is erased, the erase count data from the erase count storage region indicated as valid by the region information, updates the erase count data that has been acquired to store the erase count data that has been updated in the other erase count storage region, and for the other erase count storage regions, directly stores the erase count data acquired from the erase count storage region indicated as valid by the region information in the other erase count storage region.

5. The information processing apparatus according to claim 1, wherein:

the at least one flash memory comprises a plurality of data storage regions,

the at least one flash memory further comprises a plurality of erase count storage regions and a plurality of permission information storage regions that store permission information indicating permission/prohibition of the update of the erase count data, the plurality of erase count storage regions and the plurality of permission information storage regions corresponding to the plurality of respective data storage regions, and

the control circuit updates the erase count data for the erase count storage region corresponding to the permission information storage region that stores permission information indicating permission and suppresses update of the erase count data for the erase count storage region corresponding to the permission information storage region that stores the permission information indicating prohibition.

6. The information processing apparatus according to claim 5, wherein

the processor transmits change request data to request a change in the permission information to the control circuit, and

the control circuit allows changes of the permission information when changes of the permission information from prohibition to permission have been requested by the change request data received from the processor and suppresses changes of the permission information when changes of the permission information from permission to prohibition have been requested by the change request data received from the processor.

7. The information processing apparatus according to claim 6, wherein:

the permission information storage region comprises a first permission information storage region and a second permission information storage region that store the permission information,

the at least one flash memory further comprises a region information storage region that stores region information indicating which one of the first permission information storage region and the second permission information storage region is valid, and

when the permission information is changed, the control circuit stores the permission information after the change in one of the first permission information storage region and the second permission information storage region that is not indicated as valid by the region information and updates the region information to indicate the permission information storage region as valid.

8. The information processing apparatus according to claim 1, wherein:

the at least one flash memory further comprises an upper-limit value storage region that stores an upper-limit value of the number of erasures, and

the control circuit suppresses data erasure in the data storage region when the number of erasures indicated by the erase count data exceeds the upper-limit value stored in the upper-limit value storage region.

9. The information processing apparatus according to claim 8, wherein:

the processor transmits upper-limit value change request data that requests changes in the upper-limit value to the control circuit, and

the control circuit allows changes of the upper-limit value when changes to decrease the upper-limit value have been requested by the upper-limit value change request data received from the processor and suppresses changes of the upper-limit value when changes to increase the upper-limit value have been requested.

10. The information processing apparatus according to claim 9, wherein:

the upper-limit value storage region comprises a first upper-limit value storage region and a second upper-limit value storage region that store the upper-limit value,

the at least one flash memory further comprises a region information storage region that stores region information indicating which one of the first upper-limit value storage region and the second upper-limit value storage region is valid, and

the control circuit stores, when the upper-limit value is changed, an upper-limit value after the change in one of the first upper-limit value storage region and the second upper-limit value storage region that is not indicated as valid by the region information and updates the region information to indicate the upper-limit value storage region as valid.

11. The information processing apparatus according to claim 1, wherein:

the at least one flash memory comprises a first flash memory including a first block including the data storage region and a second flash memory including a second block including the erase count storage region, and

the second block is a data erasure unit having a size smaller than that of the first block.

12. A flash memory control method comprising:

receiving from a processor a data change request for at least one flash memory, the flash memory comprising a data storage region that stores data and an erase count storage region that stores erase count data indicating the number of times that the data is erased in the data storage region, and

changing the data when the data storage region is specified by the data change request as a target to be changed and not changing the erase count data when the erase count storage region is specified by the data change request as the target to be changed.