FLASH MEMORY SYSTEM AND OPERATING METHOD THEREOF

• US 20160210190A1
• Filed: 07/17/2015
• Published: 07/21/2016
• Est. Priority Date: 01/21/2015
• Status: Active Grant

• Current Assignee: Korea Advanced Institute of Science and Technology, SK Hynix Inc.
• Original Assignee: Korea Advanced Institute of Science and Technology, SK Hynix Inc.
• Inventors: HA, Jeong-Seok, KIM, Dae-Sung, JEONG, Su-Hwang
• Granted Patent: US 9,710,327 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 29/42 using error correcting codes [ECC] or parity check
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: H03M 13/152 Bose-Chaudhuri-Hocquenghem [BCH] codes
• CPC Class Codes: H03M 13/2906 using block codes H03M13/2957 takes precedence
• CPC Class Codes: H03M 13/2912 omitting parity on parity
• CPC Class Codes: H03M 13/2927 Decoding strategies
• CPC Class Codes: H03M 13/2963 Turbo-block codes, i.e. turbo codes based on block codes, e.g. turbo decoding of product codes
• CPC Class Codes: H03M 13/453 wherein the candidate code words are obtained by an algebraic decoder, e.g. Chase decoding

Abstract

An operation method of a flash memory system includes: performing hard decision decoding on a codeword, which is encoded in units of message blocks with row constituent codes and column constituent codes according to a block-wise concatenated BCH (BC-BCH) method; identifying a location of an error message block to which the hard decision decoding fails among a plurality of the message blocks, when the hard decision decoding fails; generating soft decision information corresponding to the row constituent codes and the column constituent codes of the error message block; and performing soft decision decoding on the error message block based on the soft decision information.

Claims

1. An operation method of a flash memory system having a controller and a memory device, the operation method comprising:

performing hard decision decoding on a codeword, which is encoded in units of message blocks with row constituent codes and column constituent codes according to a block-wise concatenated BCH (BC-BCH) method;

identifying a location of an error message block to which the hard decision decoding fails among a plurality of the message blocks, when the hard decision decoding fails;

generating soft decision information corresponding to the row constituent codes and the column constituent codes of the error message block; and

performing soft decision decoding on the error message block based on the soft decision information.

2. The operation method of claim 1, wherein the soft decision decoding includes a turbo BC-BCH code.

3. The operation method of claim 1, wherein the soft decision information is generated using a reference voltage for the error message block.

4. The operation method of claim 1, wherein the performing of the soft decision decoding comprises:

generating second extrinsic information by decoding the soft decision information and first extrinsic information corresponding to the row constituent codes of the error message block; and

generating third extrinsic information by decoding the soft decision information corresponding to the column constituent codes and the second extrinsic information.

5. The operation method of claim 4, wherein the first extrinsic information includes initial extrinsic information and a default value.

6. The operation method of claim 4, wherein the generating of the second extrinsic information comprises:

arranging a plurality of bits, which are obtained through a sum of the soft decision information corresponding to the row constituent code of the error message block and the first extrinsic information, in ascending order;

obtaining a test pattern by selecting bits having lower reliability;

obtaining a candidate codeword group by performing an XOR operation on the test pattern and the bits having lower reliability;

determining a first codeword using the candidate codeword group and the soft decision information;

obtaining a competition codeword group, which does not correspond to the first codeword among the candidate codeword group;

determining a second codeword using the competition codeword group and the soft decision information; and

obtaining the second extrinsic information through the first codeword and the second codeword.

7. The operation method of claim 6, wherein the test pattern is obtained by selecting bits having lower reliability and performing chase decoding.

8. The operation method of claim 6, wherein, in the determining of the first codeword, Euclidean distances are obtained using the candidate codeword and the soft decision information and the smallest one of the Euclidean distances is selected.

9. The operation method of claim 6, wherein, in the determining of the second codeword, Euclidean distances are obtained using the competition codeword and the soft decision information and the smallest one of the Euclidean distances is selected.

10. The operation method of claim 6, wherein, in the obtaining of the second extrinsic information, the second extrinsic information is obtained using Equation 1.

11. The operation method of claim 4, wherein the generating of the third extrinsic information comprises:

arranging a plurality of bits, which are obtained through a sum of the soft decision information corresponding to the column constituent code of the error message block and the second extrinsic information, in ascending order;

obtaining a test pattern by selecting bits having lower reliability;

obtaining a candidate codeword group by performing an XOR operation on the test pattern and the bits having lower reliability;

determining a first codeword using the candidate codeword group and the soft decision information;

obtaining a competition codeword group, which does not correspond to the first codeword among the candidate codeword group;

determining a second codeword using the competition codeword group and the soft decision information; and

obtaining the third extrinsic information through the first codeword and the second codeword.

12. The operation method of claim 11, wherein the test pattern is obtained by selecting bits having lower reliability and performing chase decoding.

13. The operation method of claim 11, wherein, in the determining of the first codeword, Euclidean distances are obtained using the candidate codeword and the soft decision information and the smallest one of the Euclidean distances is selected.

14. The operation method of claim 11, wherein, in the determining of the second codeword, Euclidean distances are obtained using the competition codeword and the soft decision information and the smallest one of the Euclidean distances is selected.

15. The operation method of claim 11, wherein, in the obtaining of the third extrinsic information, the third extrinsic information is obtained using Equation 2.

17. The flash memory system of claim 1, wherein the soft decision decoding includes a turbo BC-BCH code.

16. A flash memory system comprising:

a controller; and

a memory device,

wherein the controller comprises;

a first means for performing hard decision decoding on a codeword, which is encoded in units of message blocks with row constituent codes and column constituent codes according to a block-wise concatenated BCH (BC-BCH) method;

a second means for identifying a location of an error message block on which the hard decision decoding fails;

a third means for generating soft decision information corresponding to the row constituent codes and the column constituent codes of the error message block; and

a fourth means for performing soft decision decoding on the error message block based on the soft decision information.

18. The flash memory system of claim 16, wherein the fourth means comprises:

a fifth means for generating second extrinsic information by decoding the soft decision information and first extrinsic information corresponding to the row constituent codes of the error message block; and

a sixth means for generating third extrinsic information by decoding the soft decision information corresponding to the column constituent codes and the second extrinsic information.

19. The flash memory system of claim 18, wherein the fifth step comprises:

a seventh means for arranging a plurality of bits, which are obtained through a sum of the soft decision information corresponding to the row constituent code of the error message block and the first extrinsic information, in ascending order;

an eighth means for obtaining a test pattern by selecting bits having lower reliability;

a ninth means for obtaining a candidate codeword group by performing an XOR operation on the test pattern and the bits having lower reliability;

a tenth means for determining a first codeword using the candidate codeword group and the soft decision information;

an eleventh means for obtaining a competition codeword group that does not correspond to the first codeword among the candidate codeword group;

a twelfth means for determining a second codeword using the competition codeword group and the soft decision information; and

a thirteenth means for obtaining the second extrinsic information through the first codeword and the second codeword.

20. The flash memory system of claim 18, wherein the sixth step comprises:

a fourteenth means for arranging a plurality of bits, which are obtained through a sum of the soft decision information corresponding to the column constituent code of the error message block and the second extrinsic information, in ascending order;

a fifteenth means for obtaining a test pattern by selecting bits having lower reliability;

a sixteenth means for obtaining a candidate codeword group by performing an XOR operation on the test pattern and the bits having lower reliability;

a seventeenth means for determining a first codeword using the candidate codeword group and the soft decision information;

an eighteenth means for obtaining a competition codeword group that does not correspond to the first codeword;

a nineteenth means for determining a second codeword using the competition codeword group and the soft decision information; and

a twentieth means for obtaining the third extrinsic information through the first codeword and the second codeword.