ACCELERATING CACHE STATE TRANSFER ON A DIRECTORY-BASED MULTICORE ARCHITECTURE
First Claim
1. A method to accelerate a cache state transfer in a multicore processor, the method comprising:
- initiating a migration of a thread that executes on a first core at a first tile in the multicore processor from the first tile to a second tile in the multicore processor,wherein the first tile includes the first core and a first directory that maps a first set of block addresses and a first cache, andwherein the second tile includes a second core and a second directory that maps a second set of block addresses and a second cache,determining block addresses of blocks to be transferred from the first cache to the second cache based on the migration of the thread that executes on the first core at the first tile to the second tile in the multicore processor,identifying a third tile in the multicore processor, wherein the third tile includes a third directory that maps a third set of block addresses;
updating the third directory to reflect that the second cache shares the blocks by sending a message from the first tile to the third tile;
transferring the blocks from the first cache in the first tile to the second cache in the second tile to complete the migration of the thread from the first tile to the second tile;
using a transfer status table to maintain first status information on the update of the third directory and second status information on the transfer of the blocks from the first cache to the second cache; and
based on the first status information and the second status information maintained in the transfer status table, determining whether to send at least one of an invalidation request or an intervention request from the first tile to the second tile.
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Accused Products
Abstract
Technologies are generally described herein for accelerating a cache state transfer in a multicore processor. The multicore processor may include first, second, and third tiles. The multicore processor may initiate migration of a thread executing on the first core at the first tile from the first tile to the second tile. The multicore processor may determine block addresses of blocks to be transferred from a first cache at the first tile to a second cache at the second tile, and identify that a directory at the third tile corresponds to the block addresses. The multicore processor may update the directory to reflect that the second cache shares the blocks. The multicore processor may transfer the blocks from the first cache in the first tile to the second cache in the second tile effective to complete the migration of the thread from the first tile to the second tile.
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Citations
20 Claims
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1. A method to accelerate a cache state transfer in a multicore processor, the method comprising:
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initiating a migration of a thread that executes on a first core at a first tile in the multicore processor from the first tile to a second tile in the multicore processor, wherein the first tile includes the first core and a first directory that maps a first set of block addresses and a first cache, and wherein the second tile includes a second core and a second directory that maps a second set of block addresses and a second cache, determining block addresses of blocks to be transferred from the first cache to the second cache based on the migration of the thread that executes on the first core at the first tile to the second tile in the multicore processor, identifying a third tile in the multicore processor, wherein the third tile includes a third directory that maps a third set of block addresses; updating the third directory to reflect that the second cache shares the blocks by sending a message from the first tile to the third tile; transferring the blocks from the first cache in the first tile to the second cache in the second tile to complete the migration of the thread from the first tile to the second tile; using a transfer status table to maintain first status information on the update of the third directory and second status information on the transfer of the blocks from the first cache to the second cache; and based on the first status information and the second status information maintained in the transfer status table, determining whether to send at least one of an invalidation request or an intervention request from the first tile to the second tile. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A multicore processor, comprising:
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a first tile comprising a first core, a first cache, and a first directory that maps a first set of block addresses; a second tile comprising a second core, a second cache, and a second directory that maps a second set of block addresses; a third tile comprising a third core, a third cache, and a third directory that maps a third set of block addresses; and a transfer status table operatively coupled to at least the first tile, wherein the multicore processor is configured to; initiate a migration of a thread that executes on the first core in the first tile to the second tile; determine block addresses of blocks to be transferred from the first cache to the second cache based on the migration of the thread that executes on the first core in the first tile to the second tile; update the third directory to reflect that the second cache shares the blocks; transfer the blocks from the first cache in the first tile to the second cache in the second tile to complete the migration of the thread from the first tile to the second tile; use the transfer status table to maintain first status information on the update of the third directory and second status information on the transfer of the blocks from the first cache to the second cache; and based on the first status information and the second status information maintained in the transfer status table, determine whether to send at least one of an invalidation request or an intervention request from the first tile to the second tile. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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18. A computer-readable storage device having instructions stored thereon to accelerate a cache state transfer in a multicore processor, the instructions being executable by the multicore processor to perform or cause to be performed operations comprising:
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initiating a migration of a thread that executes on a first core at a first tile in the multicore processor from the first tile to a second tile in the multicore processor, wherein the first tile includes the first core and a first directory that maps a first set of block addresses and a first cache, and wherein the second tile includes a second core and a second directory that maps a second set of block addresses and a second cache; determining block addresses of blocks to be transferred from the first cache to the second cache based on the migration of the thread executing on the first core at the first tile to the second tile in the multicore processor; identifying a third tile in the multicore processor, wherein the third tile includes a third directory that maps a third set of block addresses; updating the third directory to reflect that the second cache shares the blocks; transferring the blocks from the first cache in the first tile to the second cache in the second tile; using a transfer status table to maintain first status information on the update of the third directory and second status information on the transfer of the blocks from the first cache to the second cache; and based on the first status information and the second status information maintained in the transfer status table, determining whether to send at least one of an invalidation request or an intervention request from the first tile to the second tile. - View Dependent Claims (19, 20)
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Specification