OPERATION MODES FOR AN INVERTED NAND ARCHITECTURE

• US 20160211023A1
• Filed: 03/28/2016
• Published: 07/21/2016
• Est. Priority Date: 12/01/2014
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Zhang, Yanli, Samachisa, George, Alsmeier, Johann, Chen, Jian
• Granted Patent: US 9,672,916 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

Methods for performing memory operations on a memory array that includes inverted NAND strings are described. The memory operations may include erase operations, read operations, programming operations, program verify operations, and erase verify operations. An inverted NAND string may include a string of inverted floating gate transistors or a string of inverted charge trap transistors. In one embodiment, an inverted floating gate transistor may include a tunneling layer between a floating gate of the inverted floating gate transistor and a control gate of the inverted floating gate transistor. The arrangement of the tunneling layer between the floating gate and the control gate allows electrons to be added to or removed from the floating gate via F-N tunneling between the floating gate and the control gate. The inverted NAND string may be formed above a substrate and oriented such that the inverted NAND string is orthogonal to the substrate.

Claims

1. A system, comprising:

a memory array including an inverted NAND string, the inverted NAND string includes a first transistor in series with a second transistor; and

one or more control circuits configured to determine a selected word line voltage to be applied to a selected word line within the memory array, the selected word line is connected to a control gate of the first transistor, the one or more control circuits configured to determine an unselected word line voltage to be applied to a first unselected word line within the memory array, the first unselected word line is connected to a control gate of the second transistor, the one or more control circuits configured to determine a source line voltage to be applied to a first diffusion at a source-side end of the inverted NAND string and configured to determine a bit line voltage to be applied to a second diffusion at a drain-side end of the inverted NAND string, the one or more control circuits configured to cause the selected word line voltage to be applied to the selected word line during a memory operation and the unselected word line voltage to be applied to the first unselected word line during the memory operation, the one or more control circuits configured to cause the source line voltage to be applied to the first diffusion of the inverted NAND string during the memory operation and the bit line voltage to be applied to the second diffusion of the inverted NAND string during the memory operation.

2. The system of claim 1, wherein:

the inverted NAND string includes a string of inverted floating gate transistors, the string of inverted floating gate transistors includes an inverted floating gate transistor, the inverted floating gate transistor includes a tunneling layer between a floating gate of the inverted floating gate transistor and a control gate of the inverted floating gate transistor.

3. The system of claim 1, wherein:

the inverted NAND string includes a string of inverted charge trap transistors, the string of inverted charge trap transistors includes an inverted charge trap transistor, the inverted charge trap transistor includes a tunneling layer between a charge trapping layer of the inverted charge trap transistor and a control gate of the inverted charge trap transistor.

4. The system of claim 1, wherein:

the first diffusion is of a different conductivity type than the second diffusion.

5. The system of claim 4, wherein:

the first diffusion comprises a p-type source diffusion and the second diffusion comprises an n-type drain diffusion.

6. The system of claim 1, wherein:

the memory operation comprises a p-channel read operation, the unselected word line voltage is less than the selected word line voltage, the bit line voltage is less than the source line voltage.

7. The system of claim 1, wherein:

the memory operation comprises an n-channel read operation, the unselected word line voltage is greater than the selected word line voltage, the bit line voltage is greater than the source line voltage.

8. The system of claim 1, wherein:

the memory array is monolithically formed in one or more physical levels of memory cells having active areas disposed above a silicon substrate.

9. An apparatus, comprising:

an inverted NAND string including a first memory cell transistor in series with a second memory cell transistor, the first memory cell transistor includes a tunneling layer that is directly connected to a control gate of the first memory cell transistor; and

one or more control circuits configured to determine a programming voltage to be applied to a selected word line connected to the control gate of the first memory cell transistor and determine a pass voltage to be applied to a first unselected word line connected to a control gate of the second memory cell transistor, the pass voltage is less than the programming voltage, the one or more control circuits configured to apply the programming voltage to the selected word line while applying the pass voltage to the first unselected word line during a memory operation.

10. The apparatus of claim 9, wherein:

the memory operation causes a threshold voltage of the first memory cell transistor to be reduced.

11. The apparatus of claim 9, wherein:

the one or more control circuits configured to determine a source line voltage to be applied to a first diffusion at a source-side end of the inverted NAND string and configured to determine a bit line voltage to be applied to a second diffusion at a drain-side end of the inverted NAND string.

12. The apparatus of claim 11, wherein:

the first diffusion is of a different conductivity type than the second diffusion.

13. The apparatus of claim 12, wherein:

the first diffusion comprises a p-type source diffusion and the second diffusion comprises an n-type drain diffusion.

14. The apparatus of claim 9, wherein:

the inverted NAND string includes a string of inverted floating gate transistors, the string of inverted floating gate transistors includes an inverted floating gate transistor, the inverted floating gate transistor includes a tunneling layer between a floating gate of the inverted floating gate transistor and a control gate of the inverted floating gate transistor.

15. The apparatus of claim 9, wherein:

the inverted NAND string includes a string of inverted charge trap transistors, the string of inverted charge trap transistors includes an inverted charge trap transistor, the inverted charge trap transistor includes a tunneling layer between a charge trapping layer of the inverted charge trap transistor and a control gate of the inverted charge trap transistor.

16. A method for operating a non-volatile memory, comprising:

determining a selected word line voltage to be applied to a selected word line within a memory array, the memory array includes an inverted NAND string, the inverted NAND string includes a first memory cell transistor, the selected word line is connected to a control gate of the first memory cell transistor;

determining an unselected word line voltage to be applied to a first unselected word line within the memory array, the inverted NAND string includes a second memory cell transistor, the first unselected word line is connected to a control gate of the second memory cell transistor;

determining a source line voltage to be applied to a first diffusion region at a source-side end of the inverted NAND string;

determining a bit line voltage to be applied to a second diffusion region at a drain-side end of the inverted NAND string;

applying the selected word line voltage to the selected word line during a memory operation;

applying the unselected word line voltage to the first unselected word line during the memory operation;

applying the source line voltage to the first diffusion region of the inverted NAND string during the memory operation; and

applying the bit line voltage to the second diffusion region of the inverted NAND string during the memory operation.

17. The method of claim 16, wherein:

the first diffusion region is of a different conductivity type than the second diffusion region.

18. The method of claim 17, wherein:

the first diffusion region comprises a p-type source diffusion and the second diffusion region comprises an n-type drain diffusion.

19. The method of claim 16, wherein:

the inverted NAND string includes a string of inverted floating gate transistors, the string of inverted floating gate transistors includes an inverted floating gate transistor, the inverted floating gate transistor includes a tunneling layer between a floating gate of the inverted floating gate transistor and a control gate of the inverted floating gate transistor.

20. The method of claim 16, wherein:

the inverted NAND string includes a string of inverted charge trap transistors, the string of inverted charge trap transistors includes an inverted charge trap transistor, the inverted charge trap transistor includes a tunneling layer between a charge trapping layer of the inverted charge trap transistor and a control gate of the inverted charge trap transistor.