LEVEL-OCCUPATION REDUCTION IN MLC WORDLINE FOR IMPROVED MEMORY IOPS

• US 20160211028A1
• Filed: 01/20/2015
• Published: 07/21/2016
• Est. Priority Date: 01/20/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Berman, Amit, Kong, Jun Jin, Beitler, Uri
• Granted Patent: US 9,613,664 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2207/102 Compression or decompression of data before storage
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

A method of operating a memory device is provided. The memory device includes a plurality of multi-level memory cells of which each memory cell includes L levels. Data which is expressed in a binary number is received. A P-length string is generated from the data. The P-length string is converted to a Q-length string. The Q-length string is distributed using I levels by eliminating at least one level from the L levels. P and Q represent binary bit lengths of the P-length string and the Q-length string. Q is greater than P. L represents a maximum number of levels which each multi-level memory cell has. I is smaller than L. The Q-length string is programmed into the plurality of memory cells.

Claims

1. A method of operating a memory device including a plurality of multi-level memory cells of which each memory cell includes L levels, comprising:

receiving data which is expressed in a binary number;

generating a P-length string from the data;

converting the P-length string to a Q-length string by eliminating at least one level from the L levels, wherein P and Q represent binary bit lengths of the P-length string and the Q-length string, wherein Q is greater than P and wherein L represents a maximum number of levels which each multi-level memory cell has; and

programming the Q-length string into the plurality of memory cells, wherein the Q-length string is distributed using I levels, and wherein I is smaller than L.

2. The method of claim 1, wherein P/Q is equal to or smaller than log_LI.

3. The method of claim 1, wherein the converting of the P-length string to the Q-length string is performed using a table including information of a plurality of one-to-one mapping relationships between the P-length string and the Q-length string.

4. The method of claim 1, wherein the converting of the P-length string to the Q-length string includes converting the P-length string expressed in a number of a base L to the Q-length string expressed in a number of a base I using a base conversion from the base L to the base I.

5. The method of claim 1, further comprising:

reading the Q-length string from the plurality of memory cells using (I-1) reference voltages; and

decoding the Q-length string to the P-length string.

6. The method of claim 5, wherein, the decoding of the Q-Length string is performed using the table including information of one-to-one mapping relationships between the P-length string and the Q-length string.

8. The method of claim 1, wherein the generating of the P-length string comprises:

compressing the data to a compressed data; and

encoding the compressed data by associating parity bits for the compressed data to generate the P-length string,

wherein the converting of the P-length string to the Q-length string is performed after the encoding of the compressed data.

9. The method of claim 1, wherein the generating of the P-length string comprises:

compressing the data to a compressed data,

and further comprising;

generating an X-length parity bit based on the Q-length string;

encoding the X-length parity bit to a Y-length parity bit, wherein Y is greater than X, and wherein the Y-length string is distributed, over the I levels.

10. The method of claim 9, further comprising:

programming the Y-length parity bit into the plurality of memory cells.

7. The method of claim 7, wherein the decoding of the Q-length string includes converting the Q-length string expressed in the number of the base L to the P-length string expressed in the number of the base I using a base conversion from the base I to the base L.

11. A method of programming a memory device having a plurality of multi-level memory cells, comprising:

receiving a P-length string expressed in a binary number;

encoding the P-length string to a first number expressed in base 2^m (L), wherein each multi-level memory cell includes L levels, and wherein m is equal to or greater than 2;

converting the first number to a Q-length string, wherein the Q-length string is expressed in a second number expressed in base I, wherein L is greater than I, wherein Q is greater than P, wherein P and Q represent binary bit lengths of the P-length string and the Q-length string; and

programming the Q-length string into Q/m memory cells of the plurality of multi-level memory cells, wherein the Q-length string is distributed over Q/m memory cells using I levels of each memory cell.

12. The method of claim 11, wherein the converting of the P-length string comprises:

eliminating at least one level from the L levels, wherein a number of the at least one level is (L-I).

13. The method of claim 11, wherein the converting of the P-length string is performed using a table including information of a plurality of one-to-one mapping relationships between the P-length string and the Q-length string.

14. The method of claim 11, wherein the converting of the input data includes:

iteratively performing a division operation to calculate a quotient and a remainder, wherein each division operation sets a dividend as a quotient calculated in a previous division operation, wherein the dividend is a value of the P-length string at a starting iteration of the iteratively performing the division operation, and

generating the Q-length string by concatenating the remainder generated from the iteratively performing of the division operation.

15. A memory controller for operating a nonvolatile memory device including a plurality of multi-level memory cells of which each memory cell includes L levels, comprising:

a level reduction encoder configured to convert a P-length string to a Q-length string, wherein the P-length is expressed in a number of base L, wherein the Q-length is expressed in a number of base I, wherein P and Q represent binary bit lengths of the P-length string and the Q-length string, wherein Q is greater than P, and wherein L represents a maximum number of levels which each multi-level memory cell has, and wherein I is smaller than L; and

a level reduction decoder configured to decode the Q-length string to the P-length string.

16. The memory controller of claim 15, further comprising:

a source encoder configured to receive data and to compress the data to generate an output; and

a channel encoder configured to;

receive the output from the source encoder;

generate parity bits based on the output;

associate the parity bits with the output to generate the P-length string; and

provide the P-length string to the level reduction encoder.

17. The memory controller of claim 15, wherein the level reduction encoder includes a first level reduction encoder configured to generate the Q-length string from the P-length string and a second level reduction encoder configured to generate a Y-length parity bit from an X-length parity hit,

wherein the X-length parity hit is generated from the Q-length string, wherein X-length parity hit is expressed in a number of base L, and wherein the Y-length parity hit is expressed in a number of base I.

18. The memory controller of claim 17, further comprising:

a source encoder configured to;

receive data;

compress the data to generate the P-length string; and

provide the P-length string to the first level reduction encoder;

a channel encoder configured to;

receive the Q-length string from the first level reduction encoder;

generate the X-length parity bit from the Q-length string; and

provide the X-length parity hit to the second level reduction encoder.

19. The memory controller of claim 15, wherein the level reduction encoder includes a register for storing a table including information of a plurality of one-to-one mapping relationships between the P-length string and the Q-length string.

20. The memory controller of claim 15, wherein the level reduction encoder is configured to:

iteratively performing a division operation to calculate a quotient and a remainder wherein each division operation sets the quotient calculated in a previous division operation as a dividend, wherein a value of the P-length string is the dividend in a first iteration of the iteratively performing of the division operation, and

generate the Q-length string by concatenating the remainder generated from the iteratively performing of the division operation.