INTERNAL SPACERS FOR NANOWIRE TRANSISTORS AND METHOD OF FABRICATION THEREOF
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Accused Products
Abstract
A nanowire transistor of the present description may be produced with internal spacers formed by using sacrificial spacers during the fabrication thereof. Once the nanowire transistor is formed, the sacrificial spacers, which are position between the transistor gate and the source and drains (respectively), may be removed. The sacrificial material between channel nanowires of the nanowire transistor may then be removed and a dielectric material may be deposited to fill the spaces between the channel nanowires. The dielectric material not between the channel nanowires may be removed to form the internal spacers. External spacers, which are position between the transistor gate and the source and drains (respectively), may then be formed adjacent the internal spacers and transistor channel nanowires.
53 Citations
36 Claims
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1-18. -18. (canceled)
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19. A method of forming a nanowire transistor, comprising:
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providing a microelectronic structure having; a fin structure, having a plurality of channel nanowires, disposed on a substrate; a gate structure abutting a portion of the fin structure, wherein the gate structure comprises a gate dielectric surrounds each of the plurality of the channel nanowires in the fin structure and a gate electrode abutting the gate dielectric; a sacrificial spacer abutting one end of the gate electrode, wherein the spacer abuts a portion of the fin structure that comprises the channel nanowires separated by sacrificial material; and one of a source and a drain abutting one end of the fin structure and the sacrificial spacer; removing the sacrificial spacer; removing the sacrificial material from between the channel nanowires; and depositing a dielectric material to form a spacer, wherein the dielectric material is disposed between the channel nanowires. - View Dependent Claims (20, 21, 22, 23, 24)
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25. A method of forming a nanowire transistor, comprising:
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providing a microelectronic structure having; a fin structure, having a plurality of channel nanowires, disposed on a substrate; a gate structure abutting a portion of the fin structure, wherein the gate structure comprises a gate dielectric surrounding each of the plurality of the channel nanowires in the fin structure and a gate electrode abutting the gate dielectric; a first sacrificial spacer abutting one end of the gate electrode, the first spacer abuts a portion of the fin structure that comprises the channel nanowires separated by sacrificial material; a second sacrificial spacer abutting another end of the gate electrode, the second sacrificial spacer abuts another portion of the fin structure that comprises the plurality of channel nanowires separated by the sacrificial material; a source abutting one end of the fin structure and the first sacrificial spacer; and a drain abutting an opposing end of the fin structure and the second sacrificial spacer; removing the first sacrificial spacer and the second sacrificial spacer; removing the sacrificial material from between the channel nanowires; and depositing a dielectric material to form a first spacer and a second spacer, wherein the dielectric material is disposed between the channel nanowires. - View Dependent Claims (26, 27, 28, 29, 30)
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31. A method of forming a nanowire transistor, comprising:
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forming a microelectronic substrate; forming a stacked layer on the microelectronic substrate comprising at least one sacrificial material layer and at least one channel material layer; forming at least one fin structure formed from the layered stack; forming at least two sacrificial spacers across the fin structure; forming a sacrificial gate material between the at least two sacrificial spacers; removing a portion of the fin structure external to the sacrificial gate material and the sacrificial spacers to expose portions of the microelectronic substrate; forming a source structure and a drain structure on the microelectronic substrate portions on opposing ends of the fin structure; forming an interlayer dielectric layer over the source structure and the drain structure; removing the sacrificial gate material from between the sacrificial spacers; selectively removing the sacrificial material layers from between the channel material layer to form at least one channel nanowire; forming a gate dielectric material to surround the channel nanowire between the at least two sacrificial spacers; forming a gate electrode on the gate dielectric material; removing the at least two sacrificial spacers; selectively removing the sacrificial material layers between the channel nanowires; and depositing a dielectric material to form at least one spacer, wherein the dielectric material is disposed between the channel nanowires. - View Dependent Claims (32, 33, 34, 35, 36)
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Specification