Trench Gated Power Device With Multiple Trench Width and its Fabrication Process
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Abstract
Power devices, and related process, where both gate and field plate trenches have multiple stepped widths, using self-aligned process steps.
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Citations
43 Claims
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1-32. -32. (canceled)
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33. A method of fabricating a power semiconductor device, comprising:
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etching a plurality of trenches into a semiconductor mass, using at least two sidewall spacer operation to form individual ones of said trenches with a stepped width; providing a dielectric which fills lowermost portions of first ones of said trenches, but not second ones of said trenches; forming insulated gate electrodes in said first trenches, but not in said second trenches; forming a first-conductivity-type source region and a second-conductivity-type body region in proximity to said first trenches; forming second-conductivity-type body contact regions in said sc mass adjacent said second trenches; and electrically connecting said source, gate, and body contact regions to provide an operative active device. - View Dependent Claims (34, 35, 36, 37, 38, 39, 40, 42)
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41. A method of fabricating a power semiconductor device, comprising:
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etching a plurality of trenches into a semiconductor mass, using at least two sidewall spacer operation to form individual ones of said trenches with a stepped width; providing a dielectric which fills lowermost portions of first ones of said trenches, but not second ones of said trenches; forming insulated gate electrodes in said first trenches, but not in said second trenches; forming a first-conductivity-type source region and a second-conductivity-type body region in proximity to said first trenches; forming second-conductivity-type body contact regions in said sc mass adjacent said second trenches; and electrically connecting said source, gate, and body contact regions to provide an operative active device; wherein said semiconductor mass is initially an epitaxial structure including a first-conductivity-type epitaxial layer on a first-conductivity-type substrate, and said substrate is much more heavily doped than said epitaxial layer.
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43. A method of fabricating a power semiconductor device, comprising:
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etching a plurality of trenches into a semiconductor mass, using at least two sidewall spacer operation to form individual ones of said trenches with a stepped width; providing a dielectric which fills lowermost portions of first ones of said trenches, but not second ones of said trenches; forming insulated gate electrodes in said first trenches, but not in said second trenches; forming a first-conductivity-type source region and a second-conductivity-type body region in proximity to said first trenches; forming second-conductivity-type body contact regions in said sc mass adjacent said second trenches; and electrically connecting said source, gate, and body contact regions to provide an operative active device; further comprising the additional step, before forming insulated gate electrodes in said first trenches, of forming insulated shield electrodes in said first trenches.
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Specification