Semiconductor Device with Surge Current Protection

• US 20160211660A1
• Filed: 12/19/2015
• Published: 07/21/2016
• Est. Priority Date: 12/23/2014
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Laven, Johannes Georg, Basler, Thomas, Schulze, Hans-Joachim
• Granted Patent: US 10,644,496 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 27/0255 using diodes as protective elements
• CPC Class Codes: H01L 27/0825 Combination of vertical direct transistors of the same conductivity type having different characteristics,(e.g. Darlington transistors)
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/06 characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
• CPC Class Codes: H01L 29/0611 for increasing or controlling the breakdown voltage of reverse biased devices H01L29/0661 takes precedence
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41708 Emitter or collector electrodes for bipolar transistors
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H02H 3/202 for dc systems
• CPC Class Codes: H02H 7/1225 : responsive to internal faults, e.g. shoot-through avoiding shoot-through H02M1/38
• CPC Class Codes: H02M 3/135 : using semiconductor devices only
• CPC Class Codes: H02M 7/44 : by static converters
• CPC Class Codes: H02M 7/48 : using discharge tubes with control electrode or semiconductor devices with control electrode

Abstract

A power device includes an active area having at least two switchable regions with different threshold voltages.

Claims

1. A power device, comprising:

a semiconductor substrate comprising a plurality of switchable cells defining an active area of the power device, each of the switchable cells comprising an emitter region, and a collector region;

an emitter metallization in ohmic contact with the emitter region of the switchable cells; and

a collector metallization in ohmic contact with the collector region of the switchable cells;

wherein the active area comprises first switchable regions and second switchable regions different to the first switchable region, each of the first and second switchable regions comprising at least a portion of one or more of the switchable cells;

wherein the first switchable regions have a first threshold in the range of 5 V to 10 V defining a device threshold at which the power device becomes conductive for continuously conducting a rated current of the power device between the emitter metallization and the collector metallization; and

wherein the second switchable regions have a second threshold in the range of 15 V to 25 V defining a surge threshold of the power device at which the power device becomes operable to conduct a surge current between the emitter metallization and the collector metallization, wherein the surge current of the power device is at least five times as large as the rated current of the power device.

2. The power device according to claim 1, wherein a slope of the transfer characteristics of the switchable cells arranged in the second switchable regions is higher than a slope of the transfer characteristics of the switchable cells arranged in the first switchable regions.

3. The power device according to claim 1, wherein the first switchable regions comprise a first surface area of the semiconductor substrate, the second switchable regions comprise a second surface area of the semiconductor substrate, the second surface area being equal to or larger than the first surface area.

4. The power device according to claim 1, further comprising an edge termination, wherein, when seen in a plane projection onto a main surface of the semiconductor substrate, an area ratio of an area covered by second switchable regions to an area covered by the first switchable regions is higher in an outer region of the active area near the edge termination than in an inner region of the active area, which is arranged spaced from the edge termination.

5. The power device according to claim 1, further comprising a gate bus structure in ohmic contact with a gate electrode structure of the switchable cells, wherein an area ratio of an area covered by the second switchable regions to an area covered by the first switchable regions is higher in a region near the gate bus structure than in a central region of the active area.

6. The power device according to claim 1, wherein each body region comprises a body contact region having a higher doping concentration than the body region, wherein portions of the body contact regions of the switchable cells arranged in the first switchable regions have a doping concentration which is different to a doping concentration of portions of the body contact regions of the switchable cells arranged in the second switchable regions.

7. The power device according to claim 6, wherein the portions of the body contact regions of the switchable cells arranged in the second switchable regions have a doping concentration which is higher than a doping concentration of the portions of the body contact regions of the switchable cells arranged in the first switchable regions.

8. The power device according to claim 1, wherein each body region comprises a channel region next to a gate electrode structure of the switchable cells, wherein portions of the channel regions of the switchable cells arranged in the first switchable regions have a doping concentration which is different to a doping concentration of portions of the channel regions of the switchable cells arranged in the second switchable regions.

9. The power device according to claim 8, wherein the portions of the channel regions of the switchable cells arranged in the second switchable regions have a doping concentration which is higher than a doping concentration of the portions of the channel regions of the switchable cells arranged in the first switchable regions.

10. The power device according to claim 1, wherein each switchable cell comprises a gate insulation layer between a gate electrode and the body region of that switchable cell, wherein the gate insulation layers of the switchable cells arranged in the second switchable regions have a thickness which is higher than a thickness of the gate insulation layers of the switchable cells arranged in the first switchable region.

11. The power device according to claim 1, wherein each switchable cell comprises a gate insulation layer between a gate electrode and the body region of that switchable cell, wherein the gate insulation layers of the switchable cells arranged in the first switchable regions have a dielectric constant which is different to a dielectric constant of the gate insulation layers of the switchable cells arranged in the second switchable regions.

12. The power device according to claim 1, wherein the switchable cells each comprise a gate electrode structure having floating gates.

13. A fault protecting circuit for a power system, comprising:

a power device according to claim 1, wherein the power device has a collector terminal in ohmic contact with the collector region of the power device and an emitter terminal in ohmic contact the emitter region of the power device, wherein the collector terminal and the emitter terminals are connectable with respective input terminals of a power system to be protected by the fault protecting circuit; and

a detection circuit operable to detect an overvoltage or overcurrent for the power systems, wherein the detection circuit is operable to apply a voltage equal to or higher than the second threshold of the power device to conduct a surge current between the input terminals of the power system and therefore to short the input terminals of the power system.

14. The fault protecting circuit according to claim 13, wherein the detection circuit is operable to apply a voltage equal to or higher than the second threshold if the detection circuit detects that the overcurrent lasts for more than a predetermined time.

15. The fault protecting circuit according to claim 14, wherein the predetermined time is at less than or equal to 500 μ

s.

16. The fault protecting circuit according to claim 13, wherein the fault protection circuit is a crowbar circuit.

19. A crowbar, comprising:

a first diode bridge;

a first node; and

a power device according to claim 1.

20. A chopper circuit, comprising:

a first input terminal for connecting with a power supply;

a first output terminal for connecting with a load;

a power device according to claim 1, wherein the power device electrically is connected in parallel with the first input terminal and the first output terminal.

21. A method for operating a power inverter having a bridge circuit comprising a first half-bridge comprising a high-side power device according to claim 1 connected between a first node and a high-side node of an intermediate circuit storage, and a low-side power device according to claim 1 connected between the first node and a low-side node of the intermediate circuit storage;

and at least a second half-bridge comprising a high-side power device according to claim 1 connected between a second node and the high-side node of the intermediate circuit storage, and a low-side power device according to claim 1 connected between the second node and the low-side node of the intermediate circuit storage, the method comprising;

detecting a collector-emitter voltage Vce and/or a collector current Ic;

determining whether an overcurrent or overvoltage conditions has been met; and

applying a gate voltage Vg above a surge threshold defining the onset of a surge current operation area of the respective power device.

22. The method according to claim 21, wherein it is determined whether an overcurrent or overvoltage conditions has been met if one of the following conditions holds true:

a temporal change of the collector-emitter voltage dVce/dt is below a predetermined threshold (dVce/dt)_crit;

or

a temporal change of the collector current dIc/dt is below a predetermined threshold (dIc/dt)_crit.

17. A power inverter, comprising:

a bridge circuit comprising

a first half-bridge comprising a high-side power device connected between a first node and a high-side node of an intermediate circuit storage, and a low-side power device connected between the first node and a low-side node of the intermediate circuit storage; and

at least a second half-bridge comprising a high-side power device connected between a second node and the high-side node of the intermediate circuit storage, and a low-side power device connected between the second node and the low-side node of the intermediate circuit storage;

a gate driver circuit connected with each gate of the high-side device and low-side power device of the first and second half-bridges and operable to provide each gate with a respective voltage to control operation of the respective power device, wherein the gate driver circuit is operable to provide a first voltage which is higher than a first threshold voltage of the respective power device at which the respective power device becomes conductive for continuously conducting a rated current of the respective power device, and a second voltage which is higher than a surge threshold of the respective power device, wherein the surge threshold is at least two times as high as the first threshold and defines the onset of a surge current operation area of the respective power device at which the respective power device becomes operable to conduct a surge current which is at least five times as large as the rated current of the respective power device.

18. The power inverter circuit according to claim 17, further comprising a detection circuit operable to distinguish between a short-circuit and a surge-current event in the respective half-bridge circuit, wherein the detection circuit is operable to control the gate driver circuit to provide the second voltage if the detection circuit detects the surge-current event.