Apparatus for Unconventional Non-Linear Feedback Shift Registers (NLFSRs)

• US 20160211971A1
• Filed: 01/19/2016
• Published: 07/21/2016
• Est. Priority Date: 01/20/2015
• Status: Active Grant

• Current Assignee: Ternarylogic LLC
• Original Assignee: Ternarylogic LLC
• Inventors: Lablans, Peter
• Granted Patent: US 10,084,593 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H04L 9/0643 Hash functions, e.g. MD5, SHA, HMAC or f9 MAC
• CPC Class Codes: H04L 9/065 Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3

Abstract

A sequence generator implemented on a processor that generates a sequence of signals applies a feedback shift register with feedback. A feedback loop connects at least a first and a second shift register element to last shift register element to a first shift register element of the shift register and includes at least one two-input n-state switching functions that is characterized by non-associative switching functions or switching tables. The sequence generator may be part of a scrambler, an autonomous sequence generator, a hash code generator, a communication device, and a data storage device.

Claims

1. A device to provide a sequence of signals, comprising:

a shift register with feedback with k shift register elements with k>

1 including a feedback path from a kth shift register element to a first shift register element, the shift register with feedback containing at least a feedback path that includes a first two-input binary switching device, wherein a switching performance of the first two-input binary switching device is characterized by a non-associative binary truth table selected from the group consisting of non-commutative switching function truth tables; and

an output to provide the sequence of signals.

2. The device of claim 1, further comprising:

a second two-input binary switching device being characterized by a non-associative binary truth table, selected from the group consisting of the NAND function truth table, the non-commutative switching function truth tables and a NOR function truth table.

3. The device of claim 1, wherein the shift register with feedback has a Fibonacci configuration.

4. The device of claim 1, wherein the shift register with feedback has a Galois configuration.

5. The device of claim 1, wherein the device is an autonomously running sequence generator.

6. The device of claim 1, wherein the device is a signal scrambler.

7. The device of claim 1, wherein the device is part of a hash code generator.

8. The device of claim 1, wherein:

the device is realized on a processor with a memory that stores a configuration of the shift register with feedback;

the memory storing a configuration of a second shift register with feedback, the configurations of the shift register with feedback and the second shift register with feedback being characterized by one or more parameters of which at least one parameter of the configuration of the second shift register with feedback is different from the configuration of the shift register with feedback; and

the processor is enabled to be reconfigured in accordance with the configuration of the second shift register with feedback.

9. The device of claim 8, wherein the one or more parameters are selected from the group consisting of:

number of n switching states of an n-state switching function with n being equal or greater than 2, a truth table of the n-state switching function, a feedback tap configuration and a length of the second shift register with feedback.

10. The device of claim 1, wherein the device is part of a communication device.

11. A method to provide a sequence of signals, comprising:

generating the sequence of signals with a shift register with feedback with k shift register elements with k>

1 including a feedback path between the kth shift register element and the first shift register element, the shift register with feedback containing at least a feedback path that includes a first two-input binary switching device that is characterized by a non-associative binary truth table selected from the group consisting of a NAND function truth table and non-commutative switching function truth tables; and

providing the sequence of signals on an output.

12. The method of claim 11, further comprising:

including in the shift register with feedback a second two-input binary switching device being characterized by a non-associative binary truth table selected from the group consisting of the NAND function truth table, the non-commutative switching function truth tables and a NOR function truth table.

13. The method of claim 11, the shift register with feedback further comprising at least one feedback tap with an always-on inverter.

14. The method of claim 11, wherein the shift register with feedback is part of a signal scrambler.

15. The method of claim 11, wherein the shift register with feedback is part of a hash code generator.

16. The method of claim 11, further comprising:

realizing the shift register with feedback on a processor with a memory storing a configuration of the shift register with feedback;

storing on the memory a configuration of a second shift register with feedback, each configuration being characterized by one or more parameters of which at least one parameter of the second shift register with feedback is different from the configuration of the shift register with feedback; and

reconfiguring the processor in accordance with the configuration of the second shift register with feedback.

17. The method of claim 16, wherein the one or more parameters are selected from the group consisting of:

number of n switching states of an n-state switching function with n being equal or greater than 2, a truth table of the n-state switching function, a feedback tap configuration and a length of a the second shift register with feedback.

18. The method of claim 11, wherein the shift register with feedback is part of a communication device.

19. A device, comprising:

a binary shift register with feedback with a plurality of shift register elements;

a feedback path containing a switching element that is characterized by a non-associative truth table selected from the group consisting of a NAND function and non-commutative binary switching functions; and

an output configured to generate a sequence of signals processed by the binary shift register.

20. The device of claim 19, wherein the sequence of signals is a content of the shift register.