Memory System and Memory-Control Method with a Programming Status

• US 20160217067A1
• Filed: 01/23/2015
• Published: 07/28/2016
• Est. Priority Date: 01/23/2015
• Status: Active Grant

• Current Assignee: Silicon Motion, Inc. (Silicon Motion)
• Original Assignee: Silicon Motion, Inc. (Silicon Motion)
• Inventors: Chiu, Shen-Ting
• Granted Patent: US 10,169,225 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/7207 management of metadata or control data
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

A memory system with a programming status is provided. The memory includes at least one first memory, at least one second memory and a controller. Each of the at least one first memory includes a plurality of memory regions to store data. Each of the at least one second memory includes a plurality of memory regions for programming the data from the at least one first memory. The controller is coupled to the second memory and utilized to record a programming status of the data. Whether the programming is successful or not is checked when the at least one first memory or the at least one second memory is going to be implemented by inquiring the programming status, and the at least one first memory stores the data until the programming is checked to be successful.

Claims

1. A memory system with a programming status, comprising:

at least one first memory, wherein each of the at least one first memory comprises a plurality of memory regions to store data;

at least one second memory, wherein each of the at least one second memory comprises a plurality of memory regions for programming the data from the at least one first memory; and

a controller, coupled to the second memory and utilized to record a programming status of the data, wherein whether the programming is successful or not is checked when the at least one first memory or the at least one second memory is going to be implemented by inquiring the programming status, and the at least one first memory stores the data until the programming is checked to be successful.

2. The memory system with a programming status as claimed in claim 1, wherein the programming status comprises information about the data, information about the at least one first memory and its memory region where the data is programmed from, and information about the at least one second memory and its memory region where the data is programmed to.

3. The memory system with a programming status as claimed in claim 2, wherein the programming status is updated when the at least one first memory or the at least one second memory has been implemented or when the programming status has been inquired.

4. The memory system with a programming status as claimed in claim 1, wherein each of the at least one second memory comprises a second buffer memory and a second cache memory.

5. The memory system with a programming status as claimed in claim 4, wherein when additional data is going to be written to the at least one first memory where the data is programmed from, the programming status is inquired to check whether the programming of the data is successful or not, and the additional data is different from the data.

6. The memory system with a programming status as claimed in claim 5, wherein the at least one first memory where the data is programmed from is written with the additional data when the programming of the data is successful, and the at least one first memory where the data is programmed from is not written with the additional data and stores the data when the programming of the data is not successful.

7. The memory system with a programming status as claimed in claim 5, wherein the programming status of the second cache memory is inquired when the data is programmed to the second cache memory, and the programming status of the second cache memory and the second buffer memory are inquired when the data is programmed to the second buffer memory.

8. The memory system with a programming status as claimed in claim 4, wherein when the data is going to be read from the at least one second memory where the data is programmed to, the programming status is inquired to check whether the programming of the data is successful or not.

9. The memory system with a programming status as claimed in claim 7, wherein the data of the at least one second memory where the data is programmed to is read when the programming of the data is successful, and the data of the at least one second memory where the data is programmed to is not read and the at least one first memory where the data is programmed from stores the data when the programming of the data is not successful.

10. The memory system with a programming status as claimed in claim 8, wherein the programming status of the second cache memory and the second buffer memory are inquired.

11. A memory-control method with a programming status, comprising:

recording a programming status of the data which is programmed from at least one first memory to at least one second memory;

checking whether the programming is successful or not when the at least one first memory or the at least one second memory is going to be implemented by inquiring the programming status; and

storing the data in the at least one first memory until the programming is checked to be successful.

12. The memory-control method with a programming status as claimed in claim 11, wherein the programming status comprises information about the data, information about the at least one first memory and its memory region where the data is programmed from, and information about the at least one second memory and its memory region where the data is programmed to.

13. The memory-control method with a programming status as claimed in claim 12, further comprising updating the programming status when the at least one first memory or the at least one second memory has been implemented or when the programming status has been inquired.

14. The memory-control method with a programming status as claimed in claim 12, wherein each of the at least one second memory comprises a second buffer memory and a second cache memory.

15. The memory-control method with a programming status as claimed in claim 14, further comprising when additional data different from the data is going to be written to the at least one first memory where the data is programmed from, inquiring the programming status to check whether the programming of the data is successful or not.

16. The memory-control method with a programming status as claimed in claim 15, further comprising writing the additional data to the at least one first memory where the data is programmed from when the programming of the data is successful, and not writing the additional data to the at least one first memory where the data is programmed from and storing the data by the at least one first memory where the data is programmed from when the programming of the data is not successful.

17. The memory-control method with a programming status as claimed in claim 15, further comprising inquiring the programming status of the second cache memory when the data is programmed to the second cache memory, and inquiring the programming status of the second cache memory and the second buffer memory when the data is programmed to the second buffer memory.

18. The memory-control method with a programming status as claimed in claim 14, further comprising when the data is going to be read from the at least one second memory where the data is programmed to, inquiring the programming status to check whether the programming of the data is successful or not.

19. The memory-control method with a programming status as claimed in claim 17, further comprising reading the data of the at least one second memory where the data is programmed to when the programming of the data is successful, and not reading the data of the at least one second memory where the data is programmed to and storing the data by the at least one first memory where the data is programmed from when the programming of the data is not successful.

20. The memory-control method with a programming status as claimed in claim 18, further comprising inquiring the programming status of the second cache memory and the second buffer memory.