MEMORY INITIALIZATION USING CACHE STATE

• US 20160217080A1
• Filed: 01/22/2015
• Published: 07/28/2016
• Est. Priority Date: 01/22/2015
• Status: Active Grant

• Current Assignee: Empire Technology Development LLC (Allied Inventors Management, LLC)
• Original Assignee: Empire Technology Development LLC (Allied Inventors Management, LLC)
• Inventors: Solihin, Yan
• Granted Patent: US 9,684,603 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0837 with software control, e.g. non-cacheable data
• CPC Class Codes: G06F 12/0879 Burst mode
• CPC Class Codes: G06F 12/0891 using clearing, invalidating or resetting means
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/6042 Allocation of cache space to multiple users or processors
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Techniques are generally described for cache management in a processor with a cache. In response to receiving a bulk memory modification instruction, data blocks of the cache associated with the bulk memory modification instruction may be identified. A cache coherence state of the identified data blocks may also be identified. The updated cache coherence state may be indicative of a zero value of the data blocks and the cache coherence state of the identified data blocks may be updated without modification to a cache data array.

Claims

1. A method for cache management in a processor with a cache, the method comprising:

receiving a bulk memory modification instruction;

identifying one or more data blocks of the cache associated with the bulk memory modification instruction; and

updating a cache coherence state of the identified one or more data blocks, wherein the updated cache coherence state is indicative of a zero value of the one or more data blocks, and wherein the cache coherence state of the identified one or more data blocks is updated without modification to a cache data array.

2. The method of claim 1, wherein updating the cache coherence state comprises setting the cache coherence state of the identified one or more data blocks to a modified zero (MZ) state in a cache tag array.

3. The method of claim 2, further comprising:

receiving a write instruction to write to a portion of a first data block of the one or more data blocks; and

writing to a portion of the first data block, wherein the cache data array is modified to write to the first data block.

4. The method of claim 3, further comprising:

after receiving the write instruction, evicting a victim block from the cache.

5. The method of claim 1, wherein updating the cache coherence state comprises:

storing one or more tags in a zero tag array in the cache, wherein the one or more tags correspond to the one or more data blocks.

6. The method of claim 5, wherein storing one or more tags comprises storing a first tag in the zero tag array, wherein the first tag corresponds to a first data block of the one or more data blocks and wherein the zero tag array is effective to indicate the state of the first data block as a modified zero (MZ) state.

7. The method of claim 5, wherein a tag in the zero tag array corresponds to a memory page and wherein updating the cache coherence state further comprises updating a bitmap that corresponds to the tag in the zero tag array.

8. The method of claim 7, further comprising:

receiving a write instruction to write to a first data block of the one or more data blocks;

writing to the first data block, wherein the cache data array is modified to write to the first data block; and

in response to writing to the first data block, updating the bitmap such that the bitmap is effective to identify a non-zero value for the first data block.

9. The method of claim 8, further comprising:

storing a cache tag corresponding to the first data block in the cache tag array, wherein the cache tag is effective to identify the first data block and wherein the cache tag array is effective to indicate the state of the first data block as a modified (M) state.

10. A processor, comprising:

a core;

a cache communicatively coupled to the core;

a cache controller communicatively coupled to the cache;

wherein the processor is configured to receive a bulk memory modification instruction, wherein one or more data blocks are associated with the bulk memory modification instruction; and

the cache controller is configured to;

in response to the bulk memory modification instruction, determine that the one or more data blocks are to be initialized; and

in response to the determination that the one or more data blocks are to be initialized, update a cache coherence state of the one or more data blocks, wherein the updated cache coherence state is indicative of an initialized value.

11. The processor of claim 10, wherein the processor is further configured to:

receive an instruction to write to a portion of a first data block of the one or more data blocks; and

in response to receipt by the processor of the instruction to write to the portion of the first data block, the cache controller is further configured to write to a cache data array of the processor to update the first data block.

12. The processor of claim 10, wherein the cache comprises a zero tag array.

13. The processor of claim 12, wherein a tag of the zero tag array corresponds to a memory page.

14. The processor of claim 13, wherein the zero tag array comprises a bitmap that corresponds to the tag.

15. The processor of claim 14, wherein the processor is further configured to:

receive a write instruction to write to a first data block of the one or more data blocks;

write to the first data block, wherein a cache data array is modified to write to the first data block; and

in response to execution of the write to the first data block, update the bitmap such that the bitmap is effective to identify a non-zero value for the first data block.

16. The processor of claim 10, wherein the cache controller is configured to:

store a cache tag corresponding to a first data block of the one or more data blocks in a cache data array, wherein the cache tag is effective to identify the first data block and wherein the cache data array is effective to indicate the state of the first data block as a modified (M) state.

17. A non-transitory computer-readable storage medium having stored thereon computer-readable instructions, the computer-readable instructions that in response to execution by one or more computing devices, at least cause the one or more computing devices to:

identify a bulk memory modification instruction;

identify a data block of a cache associated with the bulk memory modification instruction; and

update a cache coherence state of the identified data block, wherein the updated cache coherence state is indicative of an initialized value of the identified data block and wherein the cache coherence state of the identified data block is updated without modification to a cache data array.

18. The computer-readable storage medium of claim 17, wherein the cache coherence state is updated by storage of a tag corresponding to the identified data block in a zero tag array in the cache.

19. The computer-readable storage medium of claim 17, wherein a tag in a zero tag array is configured to store the tag for another data block corresponding to a page size of a memory page and wherein the cache coherence state is updated by a modification of a bitmap that corresponds to the tag in the zero tag array.

20. An apparatus, comprising:

a computing device with at least one processor that includes a cache and a cache controller, the computing device configured to;

receive a bulk memory modification instruction, wherein one or more data blocks are associated with the bulk memory modification instruction;

in response to the bulk memory modification instruction, determine that the one or more data blocks are to be initialized; and

in response to the determination that the one or more data blocks are to be initialized, update a cache coherence state of the one or more data blocks, wherein the updated cache coherence state is indicative of an initialized value.

21. A method for cache management in a processor with a cache, the method comprising:

receiving a bulk memory modification instruction;

identifying two or more data blocks of the cache associated with the bulk memory modification instruction; and

updating a cache coherence state of the identified two or more data blocks, wherein the updated cache coherence state is indicative of a zero value of the data blocks and wherein the cache coherence state of the identified two or more data blocks are updated without modification to a cache data array.

22. The method of claim 21, wherein updating the cache coherence state comprises setting the cache coherence state of the identified two or more data blocks to a modified zero (MZ) state in a cache tag array.

23. The method of claim 21, further comprising:

receiving a write instruction to write to a portion of a first data block of the two or more data blocks; and

writing to a portion of the first data block, wherein the cache data array is modified to write to the first data block a write value and pre-pending or appending the first data block with zero value data to fill a size of the first data block.