CRITICAL REGION IDENTIFICATION

• US 20160217248A1
• Filed: 04/05/2016
• Published: 07/28/2016
• Est. Priority Date: 09/09/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Antony, George, Berry, Christopher J., Nigaglioni, Ricardo H., Rangarajan, Sridhar H., Saha, Sourav, Singh, Vinay K.
• Granted Patent: US 10,140,414 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/00 Computer-aided design [CAD]
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A method and system to identify a region of a design block of an integrated circuit for redesign are described. The method includes dividing the design block into grids, each of the grids including a corresponding number of logic elements. The method also includes filtering each of the grids based on a specified criteria, the filtering including determining a number (B) of the corresponding logic elements among a total number (A) of the logic elements in each grid that meet the specified criteria. The region is a set of two or more of the grids based on a result of the filtering.

Claims

1. A processing system to identify a region of a design block of an integrated circuit for redesign, the system comprising:

a processor configured to divide the design block into grids, each of the grids including a associated number of logic elements, filter each of the grids based on a specified criticality criteria, the filtering including determining a total number (A) of the logic elements in each grid and a number (B) of the total number (A) of the logic elements in each grid that meet the specified criticality criteria, and identify the region as a set of two or more of the grids based on a result of the filtering; and

a display device configured to display the result of the filtering, wherein the processor determines, for each of the grids, a ratio as A/B and identifies the set of the two or more of the grids based on the respective ratio of the set of the two or more of the grids.

2. The system according to claim 1, wherein the processor digitizes the respective ratio for each of the grids, and the display device displays the respective ratio for each of the grids.

3. A non-transitory computer program product comprising:

a tangible storage medium readable by a processor and storing instructions for execution by the processor to perform a method of identifying a region of a design block of an integrated circuit for redesign, the method comprising;

dividing the design block into grids, each of the grids including a respective number of logic elements;

filtering each of the grids based on a specified criticality criteria, the filtering including determining a total number (A) of the logic elements in each grid and a number (B) of the total number (A) of the logic elements in each grid that meet the specified criticality criteria;

the identifying the region as a set of two or more of the grids based on a result of the filtering; and

determining, for each of the grids, a ratio as A/B and digitizing the respective ratio for each of the grids.

4. The non-transitory computer program product according to claim 3, wherein the filtering includes filtering each of the grids based on a specified timing range.