Intermediate Layer for Copper Structuring and Methods of Formation Thereof

• US 20160218033A1
• Filed: 01/28/2015
• Published: 07/28/2016
• Est. Priority Date: 01/28/2015
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Roth, Roman, Joshi, Ravi Keshav, Steinbrenner, Juergen, Fachmann, Christian, Fischer, Petra
• Granted Patent: US 9,773,736 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/32134 by liquid etching only
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 24/00 Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of forming a metallization layer over a semiconductor substrate includes depositing a blanket layer of a diffusion barrier liner over an inter level dielectric layer, and depositing a blanket layer of an intermediate layer over the diffusion barrier liner. A blanket layer of a power metal layer including copper is deposited over the intermediate layer. The intermediate layer includes a solid solution of a majority element and copper. The intermediate layer has a different etch selectivity from the power metal layer. After depositing the power metal layer, structuring the power metal layer, the intermediate layer, and the diffusion barrier liner.

Claims

1. A method of forming a metallization layer over a semiconductor substrate, the method comprising:

depositing a blanket layer of a diffusion barrier liner over an inter level dielectric layer;

depositing a blanket layer of an intermediate layer over the diffusion barrier liner;

depositing a blanket layer of a power metal layer comprising copper over the intermediate layer, wherein the intermediate layer comprises a solid solution of a majority element and copper, wherein the intermediate layer has a different etch selectivity from the power metal layer; and

after depositing the power metal layer, structuring the power metal layer, the intermediate layer, and the diffusion barrier liner.

2. The method of claim 1, wherein the majority element comprises one or more of aluminum, tungsten, titanium, nickel, manganese, molybdenum, tantalum, and silicon.

3. The method of claim 1, wherein structuring the power metal layer, the intermediate layer, and the diffusion barrier liner comprises:

forming an etch mask over the power metal layer; and

etching the power metal layer and the intermediate layer using a wet etch chemistry.

4. The method of claim 3, wherein the power metal layer is etched using a mixture comprising phosphoric acid, nitric acid, acetic acid, and wherein the intermediate layer is etched using hydrofluoric acid.

5. The method of claim 4, wherein the phosphoric acid is a majority component in the wet etch chemistry.

6. A method of forming a metallization layer over a semiconductor substrate, the method comprising:

providing a wafer comprising a layer stack comprising a diffusion barrier liner, an intermediate layer comprising aluminum, and a metal layer comprising copper; and

using wet chemical etching, forming a metal line by etching the metal layer, the intermediate layer, and the diffusion barrier liner.

7. The method of claim 6, wherein the chemistry of the wet chemical etching comprises one or more of phosphoric acid, nitric acid, acetic acid, and hydrofluoric acid, wherein the metal layer is etched using a mixture comprising phosphoric acid, nitric acid, acetic acid, and wherein the intermediate layer is etched using hydrofluoric acid.

8. The method of claim 7, wherein the phosphoric acid is a majority component in the chemistry of the wet chemical etching.

9. The method of claim 6, wherein the metal layer is at least three hundred nanometers thick.

10. The method of claim 6, wherein the intermediate layer is an aluminum layer comprising aluminum and copper.

11. The method of claim 10, wherein the aluminum layer comprises at least 50% aluminum by atomic percent.

12. The method of claim 6, wherein the intermediate layer comprises one or more of tungsten, titanium, nickel, manganese, molybdenum, tantalum, and silicon.

13. The method of claim 6, wherein the intermediate layer is an aluminum silicon copper layer comprising aluminum, silicon, and copper.

14. The method of claim 13, wherein the aluminum silicon copper layer comprises at least 50% aluminum by atomic percent.

15. The method of claim 13, wherein the aluminum silicon copper layer comprises between 1% to 3% silicon by atomic percent, and wherein the aluminum silicon copper layer comprises 0.1% to 1% copper by atomic percent.

16. The method of claim 6, wherein the intermediate layer further comprises an alloy with copper and a material of the diffusion barrier liner.

17. The method of claim 6, wherein the diffusion barrier liner comprises titanium, titanium nitride, tantalum, tantalum nitride, tungsten, and combinations thereof.

18. A method of forming a metallization layer over a semiconductor substrate, the method comprising:

forming a layer stack comprising a diffusion barrier liner, an intermediate layer, and a power metal layer comprising copper; and

forming a metal line by etching the power metal layer and the intermediate layer continuously using a wet chemical etching process, wherein the wet chemical etching is selective between the intermediate layer and the power metal layer, and wherein the diffusion barrier layer is a diffusion barrier to copper atoms from the power metal layer.

19. The method of claim 18, wherein forming the layer stack comprises:

sputtering atoms of aluminum, copper, and silicon to form the intermediate layer followed by sputtering copper atoms to form the power metal layer.

20. The method of claim 19, wherein the temperature of the sputtering of the atoms aluminum, copper, and silicon and the sputtering of copper atoms is between 200°

C. to about 400°

C.

21. The method of claim 18, wherein the chemistry of the wet chemical etching process comprises one or more of phosphoric acid, nitric acid, acetic acid, and hydrofluoric acid, wherein the power metal layer is etched using a mixture comprising phosphoric acid, nitric acid, acetic acid, and wherein the intermediate layer is etched using hydrofluoric acid.