3D Package With Through Substrate Vias

• US 20160218090A1
• Filed: 04/04/2016
• Published: 07/28/2016
• Est. Priority Date: 10/30/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Hsiao, Min-Chien, Yu, Chen-Hua, Lii, Mirng-Ji, Kuo, Hung-Yi, Tsai, Hao-Yi, Shih, Chao-Wen, Yu, Tsung-Yuan
• Granted Patent: US 9,530,759 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/56 Encapsulations, e.g. encapsulation layers, coatings
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 2224/02166 Collar structures
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/06181 On opposite sides of the body
• CPC Class Codes: H01L 2224/11001 Involving a temporary auxiliary member not forming part of the manufacturing apparatus, e.g. removable or sacrificial coating, film or substrate
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/14181 On opposite sides of the body
• CPC Class Codes: H01L 2224/16055 : being circular or elliptic
• CPC Class Codes: H01L 2224/16057 : in side view
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16155 : the item being non-metallic, e.g. being an insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/2919 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32145 : the bodies being stacked
• CPC Class Codes: H01L 2224/45015 : being circular
• CPC Class Codes: H01L 2224/45099 : Material
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48145 : the bodies being stacked
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/83101 : as prepeg comprising a layer connector, e.g. provided in an insulating plate member
• CPC Class Codes: H01L 2224/83424 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/83444 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/83447 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/83481 : Tantalum [Ta] as principal constituent
• CPC Class Codes: H01L 2224/83484 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/85424 : Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/85444 : Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/85447 : Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/85481 : Tantalum (Ta) as principal constituent
• CPC Class Codes: H01L 2224/85484 : Tungsten (W) as principal constituent
• CPC Class Codes: H01L 2225/06506 : Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 : Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/522 : including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5226 : Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/525 : with adaptable interconnections
• CPC Class Codes: H01L 23/528 : Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 24/00 : Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/065 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A package, comprising a substrate having electrical devices disposed at a first side of the substrate, vias extending from the first side of the substrate to a second side of the substrate opposite the first side and metallization layers disposed on the first side of the substrate. Contact pads are disposed over the first metallization layers and a protection layer is disposed over the contact pads. Post-passivation interconnects are disposed over the protection layer and extend to the contact pads through openings in the protection layer. Connectors are disposed on the PPIs and a molding compound extends over the PPIs and around the connectors.

Claims

1. A device comprising:

first integrated die including a transistor formed at a top surface of the die and a conductive through via extending from the top surface to a back surface of the die;

a metallization layer over the top surface of the die;

contact pads disposed over the metallization layer;

a protection layer disposed over the contact pads;

a first redistribution layer (RDL) disposed over the protection layer and extending to the contact pads through openings in the protection layer;

first connectors disposed over \on the first RDL;

a molding compound over the first RDL and around the first connectors;

a second RDL disposed on the bottom surface of the die and electrically connected to the conductive through via; and

a second integrated circuit die mounted to the bottom surface of the die and electrically connected to the second RDL.

2. The device of claim 1, wherein the second integrated circuit die is wire bonded to the second RDL.

3. The device of claim 1, further including a passivation layer between the protection layer and the contact pads.

4. The device of claim 1, wherein the conductive through via comprises an opening extending through the first die, a liner lining the opening, and a conductor filling the lined opening.

5. The device of claim 1, wherein the first connectors are disposed directly on the first RDL.

6. The device of claim 1, further comprising second connectors electrically connected to the second RDL.

7. The device of claim 1, wherein the first RDL includes conductive elements that extend laterally from the contact pads;

and

wherein the first connectors are laterally spaced apart from the contact pads.

8. The device of claim 1, wherein the second integrated circuit die is connected to the second RDL by way of solder balls.

9. The device of claim 1, further comprising a second conductive through via and wherein the second RDL electrically the conductive through via and the second conductive through via.

10. The device of claim 1, further comprising a contact plug electrically connecting the conductive through via to the metallization layer.

11. A package, comprising:

a substrate having a conductive through via disposed therein, the conductive through via extending from a circuit side to a back side of the substrate;

an interlayer dielectric (ILD) disposed on the circuit side of the substrate, the ILD having a contact plug that extends through the ILD and is in electrical contact with the conductive through via;

a top metallization layer over the ILD, the top metallization layer having a first conductive element disposed in an intermetal dielectric layer, the first conductive element being in electrical contact with the contact plug;

an insulating layer disposed on the metallization layer, the insulating layer having an opening exposing the first conductive element;

a contact pad disposed over the insulating layer and in electrical contact with the first conductive element;

a first redistribution layer (RDL) disposed over the contact pad and extending laterally from the contact pad;

a second RDL disposed over the backside of the substrate and in electrical contact with the conductive through via; and

a device electrically mounted to the second RDL.

12. The package of claim 11, wherein the device is an integrated circuit that is wire bonded to the second RDL.

13. The package of claim 11, wherein the device is a component selected from the group consisting of a wafer, a die, a substrate, and a printed circuit board (PCB).

14. The package of claim 11, further comprising a molding compound disposed around the connector and covering a portion of the first RDL, wherein the connector extends past a surface of the molding compound.

15. The package of claim 11, wherein the device is an integrated circuit die that is electrically mounted to the second RDL by way of solder balls.

16. The package of claim 11, wherein the contact pads are disposed directly on the insulating layer, and wherein the contact pad has a portion extending through an opening in the insulating layer and contacting the first conductive element in the metallization layer.

17. The package of claim 11, further comprising a protection layer disposed on the insulating layer and extending over the contact pads, wherein the interconnects are disposed directly on the protection layer.

18. A method, comprising:

forming a hole from a top surface of a back surface of a substrate;

lining the hole with a liner;

filling the lined hole with a conductor to form a through substrate via;

forming at least one transistor at the top surface of the substrate;

depositing an inter level dielectric layer on the top surface and forming a contact plug therein, the contact plug being electrically connected to the through substrate via;

depositing an inter metal dielectric layer over the inter level dielectric layer, patterning the inter metal dielectric layer with trenches and filling the trenches with conductive material;

covering the filled trenches with a patterned insulating layer, the patterned insulating layer having openings therein exposing the filled trenches;

connecting contact pads to the filled trenches by way of the openings;

forming a redistribution layer (RDL) over the patterned insulating layer, the RDL extending laterally over a major surface of the insulating layer and electrically contacting the contact pads;

adhering respective connectors to respective contact pads; and

encapsulating peripheral portions of the connectors and portions of the RDL in a molding compound.

19. The method of claim 18, further comprising forming a protection layer on the RDL, wherein the interconnects are formed directly on the protection layer and extend through openings in the protection layer to contact the contact pads.

20. The method of claim 18, further comprising forming a second RDL over the back surface of the substrate.