BARRIER LAYER ABOVE ANTI-PUNCH THROUGH (APT) IMPLANT REGION TO IMPROVE MOBILITY OF CHANNEL REGION OF FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE STRUCTURE

• US 20160218104A1
• Filed: 01/28/2015
• Published: 07/28/2016
• Est. Priority Date: 01/28/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: CHENG, Ya-Yun, WEN, Tsung-Yao, WANG, Sheng-Chen, YEONG, Sai-Hooi, SUNG, Hsueh-Chang
• Granted Patent: US 9,953,836 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1033 with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with channel and gate aligned in the lengthwise direction H01L29/42376; with buried channel H01L29/7838
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A fin field device structure and method for forming the same are provided. The FinFET device structure includes a substrate and a fin structure extending from the substrate. The FinFET device structure also includes an anti-punch through implant (APT) region formed in the fin structure and a barrier layer formed on the APT region. The barrier layer has a middle portion and a peripheral portion, and the middle portion is higher than the peripheral portion. The FinFET device structure further includes an epitaxial layer formed on the barrier layer.

Claims

1. A fin field effect transistor (FinFET) device structure, comprising:

a substrate;

a fin structure extending from the substrate;

an anti-punch through implant (APT) region formed in the fin structure;

a barrier layer formed on the APT region, wherein the barrier layer has a middle portion and a peripheral portion, and the middle portion is higher than the peripheral portion; and

an epitaxial layer formed on the barrier layer.

2. The fin field effect transistor (FinFET) device structure as claimed in claim 1, wherein the barrier layer has convex structure.

3. The fin field effect transistor (FinFET) device structure as claimed in claim 1, wherein the barrier layer comprises silicon carbide (SiC) or silicon germanium carbide (SiGeC).

4. The fin field effect transistor (FinFET) device structure as claimed in claim 1, wherein the barrier layer is epitaxially grown along the (111) plane.

5. The fin field effect transistor (FinFET) device structure as claimed in claim 1, further comprising:

an isolation structure formed on the substrate, wherein the fin structure is embedded in the isolation structure, and the APT region is below a top surface of the isolation structure.

6. The fin field effect transistor (FinFET) device structure as claimed in claim 1, further comprising:

a liner formed on the sidewalls of the fin structure.

7. The fin field effect transistor (FinFET) device structure as claimed in claim 1, wherein the epitaxial layer comprises silicon germanium (SiGe), germanium (Ge) or combinations thereof.

8. The fin field effect transistor (FinFET) device structure as claimed in claim 1, wherein the middle portion has a raised height over a top surface of the APT region, and the raised height is in a range from about 5 nm to about 10 nm.

9. A fin field effect transistor (FinFET) device structure, comprising:

a substrate;

a first fin structure and a second fin structure formed on the substrate;

a first an anti-punch through implant (APT) region formed in the first fin structure;

a barrier layer formed on the first APT region, wherein the barrier layer has a convex structure; and

an epitaxial layer formed on the barrier layer; and

a second APT region formed in the second fin structure.

10. The fin field effect transistor (FinFET) device structure as claimed in claim 9, wherein the barrier layer has a middle portion and a peripheral portion, and the middle portion is higher than the peripheral portion.

11. The fin field effect transistor (FinFET) device structure as claimed in claim 9, wherein the first fin structure is configured to form a p-type FinFET, and the second fin structure is configured to form an n-type FinFET.

12. The fin field effect transistor (FinFET) device structure as claimed in claim 9, wherein the epitaxial layer comprises silicon germanium (SiGe), germanium (Ge) or combinations thereof.

13. The fin field effect transistor (FinFET) device structure as claimed in claim 9, further comprising:

an isolation structure formed on the substrate, wherein the first fin structure is embedded in the isolation structure, and the first APT region is below a top surface of the isolation structure.

14. The fin field effect transistor (FinFET) device structure as claimed in claim 13, wherein the second APT region is higher than the top surface of the isolation structure.

15. The fin field effect transistor (FinFET) device structure as claimed in claim 9, wherein the barrier layer is epitaxially grown along the (111) plane.

16. The fin field effect transistor (FinFET) device structure as claimed in claim 9, further comprising:

a gate dielectric layer formed on the epitaxial layer; and

a gate electrode layer formed on the gate dielectric layer.

17. A method for forming a fin field effect transistor (FinFET) device structure, comprising:

providing a substrate;

forming a fin structure on the substrate;

forming an anti-punch through implant (APT) region formed in the fin structure;

forming a barrier layer on the APT region, wherein the barrier layer has a middle portion and a peripheral portion, and the middle portion is higher than the peripheral portion; and

forming an epitaxial layer on the barrier layer.

18. The method for forming the fin field effect transistor (FinFET) device structure as claimed in claim 17, wherein forming the barrier layer on the APT region comprises performing an epitaxial process on the APT region.

19. The method for forming the fin field effect transistor (FinFET) device structure as claimed in claim 18, wherein the forming the barrier layer and forming the epitaxial layer are performed in-situ in a chamber.

20. The method for forming the fin field effect transistor (FinFET) device structure as claimed in claim 17, further comprising:

forming a gate dielectric layer on the epitaxial structure; and

forming a gate electrode layer on the gate dielectric layer.