SIGNAL PROCESSING APPARATUS AND METHOD

• US 20160218732A1
• Filed: 12/30/2015
• Published: 07/28/2016
• Est. Priority Date: 01/27/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd., The Industry & Academic Cooperation In Chungnam National University
• Original Assignee: Samsung Electronics Co. Ltd., The Industry & Academic Cooperation In Chungnam National University
• Inventors: KIM, Ji-Hoon, KIM, JongPal
• Granted Patent: US 9,509,328 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03M 1/1225 using time-division multiplexing
• CPC Class Codes: H03M 1/124 Sampling or signal conditioning arrangements specially adapted for A/D converters

Abstract

A signal processing apparatus and a method are disclosed, in which the signal processing apparatus may convert an analog signal to a digital signal and store the digital signal. The signal processing apparatus may convert analog signals, transmitted by multiple analog channels, to digital signals using analog-to-digital converters (ADCs), hold the digital signals for a predetermined holding time, sequentially read the held digital signals for each digital channel, and store the sequentially read digital signals.

Claims

1. A signal processing apparatus, comprising:

a signal converter configured to convert analog signals to respective digital signals;

digital channels configured to respectively output digital channel signals derived from the digital signals; and

a digital signal arbiter configured to respectively hold each of the digital channel signals for a predetermined holding time, sequentially read the respectively held digital channel signals from each digital channel, and output the read digital channel signals.

2. The apparatus of claim 1, wherein the signal converter comprises:

analog-to-digital converters (ADCs) configured to respectively convert analog signals transmitted by analog channels to the digital signals;

an ADC processor configured to generate a valid output notification signal indicating whether an output from one of the ADCs is a valid digital signal for a target digital channel, from among the digital channels; and

a digital channel processor configured to selectively output a digital signal, derived from the digital signals, to the target digital channel, based on the generated valid output notification signal.

3. The apparatus of claim 2, wherein the digital signal arbiter is configured to generate a read signal, based on a clock signal, to control a reading of each digital channel signal from the digital channels, and

wherein the digital signal arbiter is configured to selectively read one of the digital channel signals from the digital channels based on the read signal, and output the selectively read digital channel signal.

4. The apparatus of claim 1, wherein a minimum cycle, among respective cycles of the digital channel signals, is greater than a result of a multiplying of a cycle of a clock signal and a total number of the digital channel signals.

5. The apparatus of claim 1, wherein the digital signal arbiter comprises a packet data generator configured to generate packet data comprising data of one of the digital channel signals and an identifier identifying a digital channel that provides the one digital channel signal.

6. The apparatus of claim 1, wherein the predetermined holding time is determined based on a cycle of a clock signal and a total number of the digital channel signals.

7. A signal processing apparatus, comprising:

analog-to-digital converters (ADCs) configured to respectively convert analog signals transmitted by analog channels to digital signals;

an ADC processor configured to generate a valid output notification signal indicating whether an output from one of the ADCs is a valid digital signal for a target digital channel, from among plural digital channels; and

a digital channel processor configured to selectively output a digital signal, derived from the digital signals, to the target digital channel, based on the generated valid output notification signal.

8. The apparatus of claim 7, further comprising:

a digital signal arbiter configured to respectively hold each digital signal from the digital channels for a predetermined holding time, sequentially read each of the respectively held digital signals from the digital channels, and output the read digital signals.

9. The apparatus of claim 7, wherein the digital channel processor is configured to derive the digital signal by separating, from at least one of the digital signals, one or more digital signals set for output to the target digital channel.

10. The apparatus of claim 7, wherein the ADC processor is configured to generate the valid output notification signal based on a received first connection control signal comprising connection information on a connection between an analog channel and the one ADC, and a received signal conversion notification signal indicating completion of a corresponding signal conversion performed by the one ADC.

11. The apparatus of claim 10, wherein the ADC processor comprises:

a first flip-flop configured to delay a value of the first connection control signal in response to a sampling control signal of the one ADC and to output the delayed value; and

a second flip-flop configured to generate the valid output notification signal based on the received signal conversion notification signal and the delayed value of the first connection control signal output by the first flip-flop.

12. The apparatus of claim 7, wherein the digital channel processor comprises:

a digital channel controller configured to select a digital signal, from the digital signals, to be output to the target digital channel based on respective valid output notification signals generated by a plurality of ADC processors.

13. The apparatus of claim 12, wherein the digital channel processor further comprises:

a logic gate configured to output, to a flip-flop, a result of a logical operation on the valid output notification signals; and

the flip-flop configured to generate the digital signal, derived from the digital signals, to be output through the target digital channel, based on an output signal of the logic gate.

14. A signal processing method, comprising:

holding digital signals, respectively set to be output from digital channels, for a predetermined holding time; and

sequentially reading the held digital signals based on which digital channel each held digital signal is set to be output to, and outputting the read digital signals.

15. The method of claim 14, wherein the outputting comprises:

generating a read signal, based on a clock signal, to control the sequential reading of the held digital signals; and

reading one of the held digital signals from one of the digital channels as indicated by the read signal and outputting the read digital signal.

16. The method of claim 15, wherein the outputting comprises:

generating packet data comprising the read digital signal and an identifier identifying the one digital channel.

17. The method of claim 14, wherein a minimum cycle among cycles of the digital signals is greater than a result of a multiplying of a cycle of a clock signal and a total number of the digital channels.

18. A non-transitory computer-readable storage medium comprising processing instructions to cause at least one processing device to implement the method of claim 14.

19. A signal processing method, comprising:

converting, by an analog-to-digital converter (ADC), an analog signal transmitted by an analog channel to a digital signal;

generating a valid output notification signal indicating whether the digital signal is a valid digital signal for a target digital channel;

selecting a digital signal to be output to the target digital channel from among digital signals respectively output from a plurality of ADCs, including the ADC, based on the valid output notification signal; and

outputting the selected digital signal to the target digital channel.

20. The method of claim 19, wherein the generating of the valid output notification signal comprises generating the valid output notification signal based on a first connection control signal comprising connection information on a connection between the analog channel and the ADC, and a signal conversion notification signal indicating completion of the converting performed by the ADC, and

wherein the selecting of the digital signal comprises selecting the digital signal to be output to the target digital channel from among the digital signals output from the ADCs based on valid output notification signals.