METHOD OF WAFER-LEVEL HERMETIC PACKAGING WITH VERTICAL FEEDTHROUGHS

• US 20160221824A1
• Filed: 09/11/2013
• Published: 08/04/2016
• Est. Priority Date: 09/11/2013
• Status: Active Grant

• Current Assignee: Mikrosistemler Sanayi VE Ticaret Limited Sirketi
• Original Assignee: Tayfun Akin
• Inventors: Alper, Said Emre, TORUNBALCI, Mustafa Mert, AKIN, Tayfun
• Granted Patent: US 9,556,020 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: B81B 2207/095 through the lid
• CPC Class Codes: B81C 1/00301 Connecting electric signal lines from the MEMS device with external electrical signal lines, e.g. through vias
• CPC Class Codes: B81C 2203/0118 Bonding a wafer on the substrate, i.e. where the cap consists of another wafer
• CPC Class Codes: B81C 2203/0145 Hermetically sealing an opening in the lid
• CPC Class Codes: B81C 2203/031 Anodic bondings
• CPC Class Codes: B81C 2203/035 Soldering
• CPC Class Codes: B81C 2203/036 Fusion bonding
• CPC Class Codes: B81C 2203/0792 Forming interconnections between the electronic processing unit and the micromechanical structure
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 23/02 Containers; Seals H01L23/12, H01L23/34, H01L23/48, H01L23/552, H01L23/66 take precedence; for memories G11C
• CPC Class Codes: H01L 23/04 characterised by the shape of the container or parts, e.g. caps, walls
• CPC Class Codes: H01L 23/06 characterised by the material of the container or its electrical properties
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container

Abstract

A wafer-level packaging method for MEMS structures that are desired to be encapsulated in a hermetic cavity and that need the transfer of at least a single or multiple electrical leads to the outside of the cavity without destroying the hermeticity of the cavity. Lead transfer is achieved using vertical feedthroughs that are patterned on the capping substrate within the same fabrication step to produce the encapsulating cavity. Furthermore, the structure of the vertical feedthroughs and via openings to reach these feedthroughs are arranged in such a way that conventional wirebonding would be sufficient to connect the vertical feedthroughs to the outer world, without a need for conductor-refill inside the via openings. The method is compatible with low-temperature thermocompression-based bonding/sealing processes using various sealing materials such as thin-film metals and alloys, and also with the silicon-glass anodic or silicon-silicon fusion bonding processes.

Claims

1. ) A method for wafer-level hermetic packaging of MEMS components (4) comprising:

Providing a first substrate (2) having a MEMS component (4), “

conductive leads”

of the MEMS component (4), anchors(10) that keep some part of the MEMS component (4) at a predefined offset from the surface of the substrate, and a sealing region (12) that completely surrounds the MEMS component (4) as well as the “

conductive leads”

,

Providing a second substrate (16) having a number of vertical feedthroughs (28) formed using the first silicon layer (18) of the substrate, a sealing wall (26) formed using the first silicon layer (18) of the substrate and completely surrounding the vertical feedthroughs (26), a roof (32) formed using the second silicon layer (22) and buried oxide layer (20) of the substrate and completely covering the region surrounded by the sealing wall (26) from the top, a number of via openings (24) formed using the second silicon layer (22) and buried oxide layer (20) of the substrate and reaching to the top surfaces of the vertical feedthroughs (28) through the roof (32), and a cavity (30) surrounded by the sealing wall (26) and the roof (32),

Bonding the sealing region (12) of the first substrate (2) to the sealing wall (26) of the second substrate (16) in such a way that the MEMS component (4) on the first substrate (2) is encapsulated in a closed volume defined by the first substrate (2) and the cavity (30) of the second substrate (16), and simultaneously, bonding the “

conductive leads”

on the first substrate (2) to the corresponding vertical feedthroughs (28) on the second substrate (16),

Forming wire bonding pads (38) on the exposed surfaces of the vertical feedthroughs (28) that are exposed to the via openings (24) on the second substrate (16).

Providing an isolation layer (58) has been deposited over the capping substrate (16) that covers the exposed surfaces of the capping substrate (16). And the via opening (24) has been refilled with an electrical conductor (60) in order to get electrical contact from the vertical feedthrough (28).

2. ) The method of claim 1 wherein the second substrate (16) is an SOI substrate comprising a first silicon layer(18), a second silicon layer (22), and a buried oxide layer (20) sandwiched between the first silicon layer (18) and second silicon layer (22),

3. ) The method of claim 1 wherein the second substrate (16) contains a getter material (34) coated at the bottom surface of the roof (32) facing the cavity (30),

4. ) The method of claim 1 wherein either the first substrate (2) or the second substrate (16) or both contain integrated circuits fabricated through a CMOS or a similar IC fabrication process,

5. ) The method of claim 1 wherein the sealing region (12) is made of glass, the sealing region (12), or the sealing wall (26), or both contain a sealing material (14) on them,

6. ) The method of claim 5 wherein bonding comprises eutectic or transient liquid phase bonding,

7. ) The method of claim 5 wherein neither the sealing region (12) nor the sealing wall (26) contains a sealing material (14) on them,

8. ) The method of claim 5 wherein bonding comprises silicon-glass anodic bonding,

9. ) The method of claim 1 wherein the sealing region (12) is made of silicon,

10. ) The method of claim 9 wherein either the sealing region (12), or the sealing wall (26), or both contain a sealing material (14) on them,

11. ) The method of claim 9 wherein bonding comprises eutectic or transient liquid phase bonding,

12. ) The method of claim 9 wherein neither the sealing region (12) nor the sealing wall (26) contains a sealing material (14) on them,

13. ) The method of claim 9 wherein bonding comprises silicon fusion bonding.

14. ) The method of claim 1 wherein an “

electrical conductor”

filled within the “

via openings”

on the “

second substrate”

to get electrical contact from the “

exposed surfaces of the vertical feedthroughs”

.