MAGNETIC MEMORY DEVICE AND MAGNETIC STORAGE METHOD

• US 20160224242A1
• Filed: 01/27/2016
• Published: 08/04/2016
• Est. Priority Date: 01/30/2015
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: OOTERA, Yasuaki, SHIMADA, Takuya, QUINSAT, Michael Amaud, OSADA, Yoshiaki, KONDO, Tsuyoshi, MORISE, Hirofumi, IWATA, Yoshihisa
• Granted Patent: US 9,886,199 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0683 Plurality of storage devices
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 19/02 using magnetic elements G11C19/14 takes precedence
• CPC Class Codes: G11C 19/0808 using magnetic domain propagation

Abstract

According to one embodiment, a magnetic memory device includes a first memory unit including a first memory array and a first drive unit, a second memory unit including a second memory array and a second drive unit, and a controller. The first memory array includes a first magnetic shift register unit. The second memory array includes a second magnetic shift register unit. The controller subdivides input data into a plurality of one-dimensional bit input arrays. The one-dimensional bit input arrays include a first array and a second array. The controller stores the first array in the first magnetic shift register unit on a last in, first out basis, and stores the second array in the second magnetic shift register unit on a last in, first out basis.

Claims

1. A magnetic memory device, comprising:

a first memory unit including a first memory array and a first drive unit;

a second memory unit including a second memory array and a second drive unit; and

a controller,

the first memory array including a first magnetic shift register unit,

the second memory array including a second magnetic shift register unit,

the controller subdividing input data into a plurality of one-dimensional bit input arrays,

the one-dimensional bit input arrays including a first array and a second array,

the controller storing the first array in the first magnetic shift register unit on a last in, first out basis, and storing the second array in the second magnetic shift register unit on a last in, first out basis.

2. The device according to claim 1, wherein each of the one-dimensional bit input arrays has a same size.

3. The device according to claim 1, wherein the controller outputs data including a portion obtained by arranging the first array stored in the first magnetic shift register unit and the second array stored in the second magnetic shift register unit.

4. The device according to claim 1, wherein

the one-dimensional bit input arrays further includes a third array and a fourth array,

the controller stores the first array in one portion of the first magnetic shift register unit on a last in, first out basis,

the controller stores the second array in one portion of the second magnetic shift register unit on a last in, first out basis,

the controller stores the third array in one other portion of the first magnetic shift register unit on a last in, first out basis, and

the controller stores the fourth array in one other portion of the second magnetic shift register unit on a last in, first out basis.

5. The device according to claim 4, wherein the controller outputs data including a portion obtained by arranging the first array stored in the one portion of the first magnetic shift register unit, the second array stored in the one portion of the second magnetic shift register unit, the third array stored in the one other portion of the first magnetic shift register unit, and the fourth array stored in the one other portion of the second magnetic shift register unit.

6. The device according to claim 1, wherein

the first magnetic shift register unit includes:

a first transistor including a first terminal, a second terminal, and a first gate;

a second transistor including a third terminal, a fourth terminal, and a second gate;

a magnetic wire including a plurality of magnetic domains, a first end portion of the magnetic wire being connected to the first terminal;

a magnetic layer electrically connected to the third terminal; and

an intermediate layer provided between the magnetic wire and the magnetic layer, and

the first drive unit includes;

a shift driver electrically connected to the second terminal;

a shift selector electrically connected to the first gate;

a read/write driver electrically connected to the fourth terminal;

a read/write selector electrically connected to the second gate; and

a magnetic wire driver connected to a first other end portion of the magnetic wire.

7. The device according to claim 6, wherein the intermediate layer is provided between the first end portion and the magnetic layer.

8. The device according to claim 6, wherein

at least one portion of the magnetic wire extends in a first direction,

a magnetization of the magnetic domain included in the at least one portion of the magnetic wire is in a first magnetization direction in a first state, the first magnetization direction intersecting the first direction, and

the magnetization of the magnetic domain included in the at least one portion of the magnetic wire is in a second magnetization direction in a second state, the second magnetization direction intersecting the first direction and being reverse of the first magnetization direction.

9. The device according to claim 6, wherein

the at least one portion of the magnetic wire extends in a first direction having a first axis as an axis,

a magnetization of the magnetic domain included in the at least one portion of the magnetic wire is in a first magnetization direction in a first state,

the magnetization of the magnetic domain included in the at least one portion of the magnetic wire is in a second magnetization direction in a second state,

the first magnetization direction intersects the first direction,

the first magnetization direction is a direction from the first axis toward a position separated from the first axis,

the second magnetization direction intersects the first direction, and

the second magnetization direction is a direction toward the first axis from a position separated from the first axis.

10. The device according to claim 1, wherein

the first memory array includes a plurality of magnetic shift register units,

the first drive unit includes a first preamplifier connected to the magnetic shift register units included in the first memory array,

the second memory array includes a plurality of magnetic shift register units, and

the second drive unit includes a second preamplifier connected to the magnetic shift register units included in the second memory array.

11. A magnetic storage method, comprising:

subdividing input data into a plurality of one-dimensional bit input arrays including a first array and a second array; and

storing the first array in a first magnetic shift register unit on a last in, first out basis, and storing the second array in a second magnetic shift register unit on a last in, first out basis,

the first magnetic shift register unit being included in a first memory array,

the second magnetic shift register unit being included in a second memory array,

the first memory array being included in a first memory unit, the first memory unit including a first drive unit,

the second memory array being included in a second memory unit, the second memory unit including a second drive unit.

12. The method according to claim 11, wherein each of the one-dimensional bit input arrays has a same size.

13. The method according to claim 11, including outputting data including a portion obtained by arranging the first array stored in the first magnetic shift register unit and the second array stored in the second magnetic shift register unit.

14. The method according to claim 11, wherein

the one-dimensional bit input arrays further include a third array and a fourth array,

the method includes:

storing the first array in one portion of the first magnetic shift register unit on a last in, first out basis;

storing the second array in one portion of the second magnetic shift register unit on a last in, first out basis;

storing the third array in one other portion of the first magnetic shift register unit on a last in, first out basis; and

storing the fourth array in one other portion of the second magnetic shift register unit on a last in, first out basis.

15. The method according to claim 13, including outputting data including a portion obtained by arranging the first array stored in the one portion of the first magnetic shift register unit, the second array stored in the one portion of the second magnetic shift register unit, the third array stored in the one other portion of the first magnetic shift register unit, and the fourth array stored in the one other portion of the second magnetic shift register unit.