LOOP STRUCTURE FOR OPERATIONS IN MEMORY

• US 20160225422A1
• Filed: 02/02/2016
• Published: 08/04/2016
• Est. Priority Date: 02/03/2015
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Wheeler, Kyle, Tiwari, Sanjay
• Granted Patent: US 9,583,163 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1036 using data shift registers
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 8/04 using a sequential addressing device, e.g. shift register, counter

Abstract

Examples of the present disclosure provide apparatuses and methods related to performing a loop structure for operations performed in memory. An example apparatus might also include a controller configured to cause sensing circuitry to iterate through a plurality of first elements and a plurality of second elements via a loop structure to perform an operation using the plurality of first elements and the plurality of second elements, wherein a conditional statement associated with the loop structure is used to determine whether at least one of a plurality of bits stored as an iterator mask has a particular bit-value. An example apparatus might also include sensing circuitry controllable to perform a shift operation using the iterator mask at each iteration of the loop structure and perform an AND operation using the iterator mask at each iteration of the loop structure.

Claims

1. An apparatus comprising:

a first group of memory cells coupled to a first access line of a memory array and configured to store a plurality of first elements;

a second group of memory cells coupled to a second access line of the memory array and configured to store a plurality of second elements; and

a controller configured to cause sensing circuitry to;

iterate through the plurality of first elements and the plurality of second elements via a loop structure to perform an operation using the plurality of first elements and the plurality of second elements;

wherein a conditional statement associated with the loop structure is used to determine whether at least one of a plurality of bits stored as an iterator mask has a particular bit-value;

perform a shift operation using the iterator mask at each iteration of the loop structure; and

perform an AND operation using the iterator mask at each iteration of the loop structure.

2. The apparatus of claim 1, wherein each of the plurality of first elements and the plurality of second elements has a same element width.

3. The apparatus of claim 1, wherein the shift operation is towards a least significant bit (LSB).

4. The apparatus of claim 1, wherein performing the shift operation at each iteration of the loop structure and the AND operation at each iteration of the loop structure comprises performing the shift operation and the AND operation without performing a sense line address access.

5. The apparatus of claim 4, further comprising performing the shift operation and the AND operation using sensing circuitry on pitch with a number of columns of complementary sense lines.

6. The apparatus of claim 5, wherein the iterator mask is stored in a third group of memory cells coupled to a third access lines.

7. The apparatus of claim 6, wherein performing the shift operation include shifting a plurality of bit-values of the plurality of bits stored as the iterator mask one position towards the LSB to an adjacent cell from the third group of memory cells.

8. The apparatus of claim 5, wherein the sensing circuitry comprises a sense amplifier and a compute component corresponding to each respective one of the number of columns of complementary sense lines.

9. The apparatus of claim 8, wherein the sense amplifier further comprises a primary latch and the compute component comprises a secondary latch.

10. A method comprising:

performing a plurality of BLOCKOR operations on an iterator mask using a loop structure to perform a particular operation using a plurality of first elements and a plurality of second elements;

wherein a first group of memory cells that are coupled to a first access line in a memory array store the plurality of first elements; and

wherein a second group of memory cells that are coupled to a second access line in the memory array store a plurality of second elements;

performing a number of logical operations at each iteration of the loop structure using the plurality of first elements and the plurality of second elements to perform the particular operation;

performing a first shift operation using the iterator mask at each iteration of the loop structure; and

performing an AND operation using the iterator mask at each iteration of the loop structure.

11. The method of claim 10, wherein each of the plurality of first elements and the plurality of second elements that the BLOCKOR is performed using has a same element width.

12. The method of claim 10, wherein performing the first shift operation comprises performing the first shift operation towards a most significant bit (MSB) using the iterator mask at each iteration of the loop structure.

13. The method of claim 10, wherein, the loop structure includes performing a plurality of loops.

14. The method of claim 13, wherein, a quantity of the plurality of loops of the loop structure is equal to a plurality of bit positions in the iterator mask.

15. The method of claim 14, wherein the iterator mask includes:

a plurality of bits associated with the plurality of first elements and the plurality of second elements;

wherein each bit in the plurality of bits included in the iterator mask corresponds with a different bit pair from each of the plurality of first elements and the plurality of second elements;

wherein the plurality of bits included in the iterator mask are grouped into a plurality of bit groups that are associated with element pairs from the plurality of first elements and the plurality of second elements; and

wherein each of the plurality of bit groups in the iterator mask have the same element width as each element in the plurality of first elements and the plurality of second elements.

16. The method of claim 15, wherein, the quantity of the plurality of loops of the loop structure is equal to the same element width associated with each of the plurality of bit groups in the iterator mask.

17. The method of claim 16, wherein, performing the first shift operation using the iterator mask includes storing a result of the first shift operation in a number of memory cells that store the iterator mask.

18. The method of claim 17, wherein, performing the AND operation includes performing the AND operation using the iterator mask and a static mask to prevent the first shift operation from shifting bits from one of the plurality of groups in the iterator mask to a different group of the plurality of groups in the iterator mask.

19. The method of claim 18, further comprising creating the row static mask by performing an invert operation using an element mask that indicates a most significant bit for each of the plurality of first elements and the plurality of second elements.

20. The method of claim 10, further comprising, creating the iterator mask from an element mask that indicates a most significant bit for each of the plurality of first elements and the plurality of second elements.

21. The method of claim 20, further comprising, creating the element mask by:

setting a plurality of bits in a bit-vector stored in a plurality of compute components coupled to a plurality of sense lines equal to one, wherein the plurality of sense lines are coupled to memory cells that store the plurality of first elements and the plurality of second elements;

performing a second shift operation towards a least significant bit (LSB) on the bit-vector stored in the plurality of compute components;

performing an invert operation using the bit-vector stored in the plurality of compute components to identify the most significant bit associated with the plurality of first elements and the plurality of second elements; and

storing the bit-vector stored in the compute components in a number of memory cells that store the element mask.

22. The method of claim 21, wherein, the element mask is further created by:

storing the element mask in the compute components;

executing a FOR loop that iterates through a plurality of elements pairs in the plurality of first elements and the plurality of second elements;

performing a third shift operation towards the LSB using the bit-vector stored in the plurality of compute components, wherein the third shift operation shifts the bit-vector stored in the plurality of compute components based on the same element width;

performing an OR operation using the bit-vector stored in the plurality of compute components and the element mast to identify the most significant bit associated with each of the plurality of first elements and the plurality of second elements; and

storing the bit-vector stored in the compute components in the number of memory cells that store the element mask.

23. The method of claim 22, wherein, the iterator mask is created by:

storing the element mask in the compute components;

performing a fourth shift operation towards the LSB on the bit-vector stored in the compute components to mark a first iteration of a number of loops associated with the loop structure; and

storing the bit-vector stored in the compute components in a number of memory cells that store the iterator mask.

24. The method of claim 23, wherein, the BLOCKOR operation determines whether one or more of the compute components store a particular bit-value.

25. An apparatus configured to perform operations in memory using a loop structure, the apparatus comprising:

a first group of memory cells coupled to a first access line in a memory array and configured to store a plurality of first elements;

a second group of memory cells coupled to a second access line in the memory array and configured to store a plurality of second elements; and

a controller configured to cause sensing circuitry to;

iterate through the plurality of first elements and the plurality of second elements via a loop structure with a BLOCKOR operation as a conditional statement to perform an operation using the plurality of first elements and the plurality of second elements;

wherein the BLOCKOR operation uses an iterator mask; and

wherein the plurality of first elements and the plurality of second elements have variable element widths;

perform a shift operation towards a least significant bit (LSB) using the iterator mask at each iteration of the loop structure; and

perform an AND operation using the iterator mask at each iteration of the loop structure.

26. The apparatus of claim 25, wherein a plurality of elements pairs are formed from the plurality of first elements and the plurality of second elements and wherein each of the plurality of first elements is associated with one of the plurality of second elements to form each of the plurality of element pairs.

27. The apparatus of claim 26, wherein elements in at least one element pair from the plurality of element pairs have a different element width as elements in at least one other element pair from the plurality of element pairs.

28. The apparatus of claim 27, wherein each element in each element pair from the plurality of element pairs has a same element width.

29. The apparatus of claim 28, wherein bit positions from the iterator mask are associated with each of the plurality of element pairs.

30. The apparatus of claim 29, wherein the AND operation prevents the first shift operation from shifting bit values, in the iterator mask, that are associated with one of the plurality of element pairs, into bit positions that are associated with a different one of the plurality of element pairs.

31. The apparatus of claim 25, wherein the sensing circuitry is further controllable by the controller to create the iterator mask by:

storing an element mask in a plurality of memory cells that store the iterator mask;

wherein the element mask identifies a most significant bit for each of the plurality of first elements and the plurality of second elements.

32. The apparatus of claim 31, wherein the sensing circuitry is further controllable by the controller to perform the AND operation using the iterator mask and a static mask that identifies all bits except the most significant bit for each of the plurality of first elements and the plurality of second elements.

33. The apparatus of claim 32, wherein the sensing circuitry is controllable by the controller to:

create the static mask by;

performing an invert operation on the element mask;

performing a second shift operation towards a most significant bit (MSB) on a result of the invert operation on the element mask; and

storing a result of the second shift operation in a group of memory cells that store the static mask.

34. A method for performing operations in memory using a loop structure, the method comprising:

performing a plurality of BLOCKOR operations on an iterator mask using a loop structure to perform a particular operation using a plurality of first elements and a plurality of second elements;

wherein the plurality of first elements and the plurality of second elements have variable element widths;

wherein a first group of memory cells that are coupled to a first access line in a memory array store the plurality of first elements; and

wherein a second group of memory cells that are coupled to a second access line in the memory array store a plurality of second elements;

performing a number of logical operations at each iteration of the loop structure using the plurality of first elements and the plurality of second elements to perform the particular operation;

performing a SHIFT operation towards a most significant bit (MSB) using the iterator mask at each iteration of the loop structure; and

performing an AND operation using the iterator mask at each iteration of the loop structure.

35. The method of claim 34, wherein the iterator mask identifies a least significant bit from each of a plurality of element pairs from the plurality of first element and the plurality of second elements, during a first iteration of the loop structure.

36. The method of claim 35, wherein the iterators mask identifies a most significant bit from at least one of the plurality of element pairs during a last iteration of the loop structure.

37. The method of claim 36, wherein the iterator mask does not identify any bits from the plurality of element pairs after performing a last BLOCKOR operation from the plurality of BLOCKOR operations.