FLASH MEMORY DEVICE

• US 20160225452A1
• Filed: 08/05/2015
• Published: 08/04/2016
• Est. Priority Date: 01/30/2015
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: LEE, Go Hyun, KIM, Jin Ho, CHA, Jae Yong
• Granted Patent: US 9,514,822 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207

Abstract

A flash memory device is disclosed. The flash memory device includes: a cell array region; an X-decoder region arranged adjacent to the cell array region in a first direction; a discharge transistor region disposed between the cell array region and the X-decoder region; a first metal line formed to pass through the X-decoder region, the discharge transistor region, and the cell array region, and arranged to extend in the first direction; and a second metal line including a first line patterns arranged parallel to the first metal line between the first metal lines, and a second line pattern interconnecting both ends of the first line patterns and extending in a second direction crossing the first direction.

Claims

1. A flash memory device comprising:

a cell array region;

an X-decoder region arranged adjacent to the cell array region in a first direction;

a discharge transistor region disposed between the cell array region and the X-decoder region;

a first metal line formed to pass through the X-decoder region, the discharge transistor region, and the cell array region, and arranged to extend in the first direction; and

a second metal line including first line patterns arranged parallel to the first metal line between the first metal lines, and a second line pattern interconnecting both ends of the first line patterns and extending in a second direction crossing the first direction.

2. The flash memory device according to claim 1, wherein the X-decoder region includes a block switch and a pass transistor.

3. The flash memory device according to claim 2, wherein the block switch and the pass transistor respectively include a block word line and a gate electrode.

4. The flash memory device according to claim 1, wherein the cell array region includes a bit line extending in the second direction.

5. The flash memory device according to claim 4, wherein the cell array region further includes:

a word line formed to extend in the first direction.

6. The flash memory device according to claim 5, wherein the word line is a multi-layered structure in which an insulation film and a conductive material are alternately stacked.

7. The flash memory device according to claim 6, further comprising:

a plurality of channel regions formed to pass through the multi-layered word line.

8. The flash memory device according to claim 7, further comprising:

a source contact plug and a drain contact plug respectively coupled to the plurality of channel regions.

9. The flash memory device according to claim 8, wherein the source contact plug is coupled to a source line, and the drain contact plug is coupled to a bit line.

10. The flash memory device according to claim 9, wherein the bit line is located at an upper level of the source line.

11. The flash memory device according to claim 1, wherein the discharge transistor region includes one or more gate electrodes and source/drain regions.

12. The flash memory device according to claim 1, wherein the first metal line is a block word line coupled to a gate electrode of a pass transistor disposed in the X-decoder region.

13. The flash memory device according to claim 1, wherein the second metal line is a source line.

14. The flash memory device according to claim 1, wherein the first metal line and the second metal line are located in the same layer.

15. The flash memory device according to claim 1, wherein the second metal line is coupled to a source line discharge transistor disposed in the discharge transistor region.

16. The flash memory device according to claim 1, wherein the second metal line is located over a bit line disposed in the cell array region.

17. The flash memory device according to claim 1, further comprising:

a third metal line formed adjacent to the cell array region in the second direction at both sides of the cell array region, and formed to extend in the first direction.

18. The flash memory device according to claim 17, wherein the third metal line is coupled to a source line discharge transistor disposed in the discharge transistor region, and receives a ground voltage as an input.

19. The flash memory device according to claim 1, wherein the first metal line is formed to interconnect a plurality of pass transistors.

20. The flash memory device according to claim 1, further comprising:

a page buffer region formed at one side of the cell region in the second direction.