SEMICONDUCTOR DEVICE
First Claim
1. A semiconductor device comprising:
- a memory array provided with electrically rewritable nonvolatile memory cells arranged in a matrix;
a driver circuit operable to drive a plurality of word lines each corresponding to a row of the memory array; and
a decode circuit operable to generate a plurality of selection signals to select each of the word lines based on a plurality of predecode signals, and operable to supply the generated selection signals to the driver circuit,wherein the decode circuit comprises;
a plurality of first logic gates each operable to invert a logical level of the corresponding predecode signal according to an operation mode;
a plurality of first level shifters each operable to convert one of the corresponding predecode signal and its inverted signal into a step-up signal of a voltage level according to the operation mode; and
a plurality of first logic circuits operable to generate the selection signal by performing a logical operation of the corresponding step-up signals among the step-up signals respectively outputted from the first level shifters, andwherein each of the first logic circuits performs a different logical operation according to the operation mode.
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Accused Products
Abstract
The number of level shifters is reduced in a decode circuit of a nonvolatile memory. A semiconductor device is configured with an electrically rewritable nonvolatile memory cell array, and a decode circuit which generates a selection signal to select a driver for a memory gate line (word line). The decode circuit includes a level shifter to step up a signal after predecode. The selection signal is generated by decoding predecode signals which are stepped up by the level shifter in the logical operation circuit. A logic gate to invert the logical level of the predecode signal depending on an operation mode is provided in the preceding stage of each level shifter. When decoding the stepped-up predecode signal, the logical operation circuit performs a different logical operation depending on the operation mode.
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Citations
14 Claims
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1. A semiconductor device comprising:
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a memory array provided with electrically rewritable nonvolatile memory cells arranged in a matrix; a driver circuit operable to drive a plurality of word lines each corresponding to a row of the memory array; and a decode circuit operable to generate a plurality of selection signals to select each of the word lines based on a plurality of predecode signals, and operable to supply the generated selection signals to the driver circuit, wherein the decode circuit comprises; a plurality of first logic gates each operable to invert a logical level of the corresponding predecode signal according to an operation mode; a plurality of first level shifters each operable to convert one of the corresponding predecode signal and its inverted signal into a step-up signal of a voltage level according to the operation mode; and a plurality of first logic circuits operable to generate the selection signal by performing a logical operation of the corresponding step-up signals among the step-up signals respectively outputted from the first level shifters, and wherein each of the first logic circuits performs a different logical operation according to the operation mode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A semiconductor device comprising:
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a memory array provided with electrically rewritable nonvolatile memory cells arranged in a matrix, wherein the memory array comprises; a plurality of word lines each corresponding to a row of the memory array, and is divided into a plurality of blocks every plurality of rows of the memory array, wherein the semiconductor device further comprises; a driver circuit operable to drive the word lines, wherein the driver circuit comprises; a plurality of driver groups respectively corresponding to the blocks, wherein each of the driver groups comprises; a first power supply line on a low potential side; a second power supply line on a high potential side; and a plurality of drivers operable to drive respectively the word lines provided in the corresponding block, wherein the semiconductor device further comprises; a first decode circuit operable to supply a first power supply potential according to the operation mode to each of the first power supply lines, based on a plurality of first predecode signals, wherein the first decode circuit comprises; a plurality of first logic gates each operable to invert a logical level of the corresponding first predecode signal according to the operation mode; a plurality of first level shifters each operable to convert one of the corresponding first predecode signal and its inverted signal into a step-up signal of a voltage level according to the operation mode; and a plurality of first logic circuits each operable to perform a logical operation of the corresponding step-up signals among the step-up signals respectively outputted from the first level shifters to generate the first power supply potential, and operable to supply the generated first power supply potential to the corresponding first power supply line, and wherein each of the first logic circuits performs a different logical operation according to the operation mode. - View Dependent Claims (13, 14)
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Specification