SEMICONDUCTOR DEVICE

• US 20160225453A1
• Filed: 12/07/2015
• Published: 08/04/2016
• Est. Priority Date: 01/29/2015
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: KASHIHARA, Yoji
• Granted Patent: US 9,558,830 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits

Abstract

The number of level shifters is reduced in a decode circuit of a nonvolatile memory. A semiconductor device is configured with an electrically rewritable nonvolatile memory cell array, and a decode circuit which generates a selection signal to select a driver for a memory gate line (word line). The decode circuit includes a level shifter to step up a signal after predecode. The selection signal is generated by decoding predecode signals which are stepped up by the level shifter in the logical operation circuit. A logic gate to invert the logical level of the predecode signal depending on an operation mode is provided in the preceding stage of each level shifter. When decoding the stepped-up predecode signal, the logical operation circuit performs a different logical operation depending on the operation mode.

Claims

1. A semiconductor device comprising:

a memory array provided with electrically rewritable nonvolatile memory cells arranged in a matrix;

a driver circuit operable to drive a plurality of word lines each corresponding to a row of the memory array; and

a decode circuit operable to generate a plurality of selection signals to select each of the word lines based on a plurality of predecode signals, and operable to supply the generated selection signals to the driver circuit,

wherein the decode circuit comprises;

a plurality of first logic gates each operable to invert a logical level of the corresponding predecode signal according to an operation mode;

a plurality of first level shifters each operable to convert one of the corresponding predecode signal and its inverted signal into a step-up signal of a voltage level according to the operation mode; and

a plurality of first logic circuits operable to generate the selection signal by performing a logical operation of the corresponding step-up signals among the step-up signals respectively outputted from the first level shifters, and

wherein each of the first logic circuits performs a different logical operation according to the operation mode.

2. The semiconductor device according to claim 1,

wherein the memory array is divided into a plurality of blocks every plurality of rows of the memory array,

wherein the driver circuit comprises:

a plurality of driver groups respectively corresponding to the blocks,

wherein each of the driver groups comprises;

a first power supply line on a low potential side;

a second power supply line on a high potential side; and

a plurality of drivers operating with a voltage supplied from the first power supply line and the second power supply line, and each operable to drive a memory cell of the corresponding row of the corresponding block,

wherein the decode circuit comprises;

a first decode circuit operable to supply a first power supply potential to the first power supply line of each of the driver groups; and

a second decode circuit operable to supply a second power supply potential to the second power supply line of each of the driver groups, and

wherein the first decode circuit comprises;

the first logic gates;

the first level shifters; and

the first logic circuits each operable to supply the first power supply potential to the corresponding first power supply line as the selection signal.

3. The semiconductor device according to claim 2,

wherein the second decode circuit comprises:

a plurality of second level shifters each operable to convert the corresponding predecode signal into a step-up signal of a voltage level according to the operation mode; and

a plurality of second logic circuits each operable to perform a logical operation of the corresponding step-up signals among the step-up signals respectively outputted from the second level shifters to generate the second power supply potential, and operable to supply the generated second power supply potential to the corresponding second power supply line as the selection signal, and

wherein each of the second logic circuits performs the same logical operation irrespective of the operation mode.

4. The semiconductor device according to claim 3,

wherein each of the drivers of each of the driver groups supplies the potential of one of the first power supply line and the second power supply line, to the corresponding word line according to a gate control signal,

wherein the decode circuit comprises:

a third decode circuit provided in common to the driver groups and operable to supply the gate control signal to each of the drivers configuring each of the driver groups,

wherein the third decode circuit comprises;

a plurality of second logic gates each operable to invert a logical level of the corresponding predecode signal according to an operation mode;

a plurality of third level shifters each operable to convert one of the corresponding predecode signal and its inverted signal into a step-up signal of a voltage level according to the operation mode; and

a plurality of third logic circuits each operable to perform a logical operation of the corresponding step-up signals among the step-up signals respectively outputted from the third level shifters to generate the gate control signal, and operable to supply the generated gate control signal to the corresponding driver as the selection signal, and

wherein each of the third logic circuits performs a different logical operation according to the operation mode.

5. The semiconductor device according to claim 1,

wherein the driver circuit comprises:

a first power supply line on a low potential side;

a second power supply line on a high potential side; and

a plurality of drivers operating with a voltage supplied from the first power supply line and the second power supply line, and each operable to drive a memory cell of the corresponding row,

wherein each of the drivers comprises;

a CMOS (Complementary Metal Oxide Semiconductor) inverter,

wherein the decode circuit comprises;

a first decode circuit operable to supply a first gate signal to a gate of an N-type transistor configuring each of the CMOS inverters; and

a second decode circuit operable to supply a second gate signal to a gate of a P-type transistor configuring each of the CMOS inverters, and

wherein the first decode circuit comprises;

the first logic gates;

the first level shifters; and

the first logic circuits operable to supply the first gate signal to the corresponding driver as the selection signal.

6. The semiconductor device according to claim 5,

wherein the second decode circuit comprises:

a plurality of second level shifters each operable to convert the corresponding predecode signal into a step-up signal of a voltage level according to the operation mode; and

a plurality of second logic circuits each operable to perform a logical operation of the corresponding step-up signals among the step-up signals respectively outputted from the second level shifters to generate the second gate signal, and operable to supply the generated second gate signal to the corresponding driver as the selection signal, and

wherein each of the second logic circuits performs the same logical operation irrespective of the operation mode.

7. The semiconductor device according to claim 1,

wherein the driver circuit comprises:

a first power supply line on a low potential side;

a second power supply line on a high potential side; and

a plurality of drivers operating with a voltage supplied from the first power supply line and the second power supply line, and each operable to drive a memory cell of the corresponding row, and

wherein each of the drivers supplies the potential of one of the first power supply line and the second power supply line, to the corresponding word line according to the corresponding selection signal.

8. The semiconductor device according to claim 2,

wherein the semiconductor device has, as the operation mode, a write mode in which data is written in the selected memory cell and an erasing mode in which the written data of the selected memory cell is erased,

wherein, in the write mode, the second decode circuit sets the second power supply potential at a higher potential than at the time of data read,

wherein, in the erasing mode, the first decode circuit sets the first power supply potential at a negative potential,

wherein the first logic gate does not invert the logical level of the corresponding predecode signal in the write mode, but inverts the logical level of the corresponding predecode signal in the erasing mode, and

wherein the first logic circuit performs an AND operation as the logical operation in the write mode, and performs an OR operation as the logical operation in the erasing mode.

9. The semiconductor device according to claim 7,

wherein the semiconductor device has, as the operation mode, a write mode in which data is written in the selected memory cell and an erasing mode in which the written data of the selected memory cell is erased,

wherein, in the write mode, the potential of the second power supply line is set at a higher potential than in reading,

wherein, in the erasing mode, the potential of the first power supply line is set at a negative potential,

wherein the first logic gate does not invert the logical level of the corresponding predecode signal in the write mode, but inverts the logical level of the corresponding predecode signal in the erasing mode, and

wherein the first logic circuit performs an NAND operation as the logical operation in the write mode, and performs an NOR operation as the logical operation in the erasing mode.

10. The semiconductor device according to claim 8,

wherein the first logic circuit comprises:

first and a second N-type transistors coupled in series between the first power supply line and an output node;

third and a fourth N-type transistors coupled in series between the first power supply line and the output node and coupled in parallel to the whole of the first and the second N-type transistors;

a fifth N-type transistor coupled in parallel with the fourth N-type transistor;

first and a second P-type transistors coupled in series between the second power supply line and the output node;

third and a fourth P-type transistors coupled in series between the second power supply line and the output node and coupled in parallel to the whole of the first and the second P-type transistors; and

a fifth P-type transistor coupled in parallel with the fourth P-type transistor,

wherein one of a first predecode signal stepped up and its inverted signal is supplied to each gate of the first and the fourth N-type transistors and the first and the fourth P-type transistors,

wherein one of the second predecode signal stepped up and its inverted signal is supplied to each gate of the second and the fifth N-type transistors and the second and the fifth P-type transistors,

wherein an inversion control signal is supplied to each gate of the third P-type transistor and the third N-type transistor, and

wherein the inversion control signal becomes a low level in the write mode, and becomes a high level in the erasing mode.

11. The semiconductor device according to claim 10,

wherein the first logic circuit further comprises:

a sixth transistor coupled between a first intermediate node between the first and the second N-type transistors, and the first power supply line;

a seventh transistor coupled between a second intermediate node between the first and the second P-type transistors, and the second P-type transistor;

an eighth transistor coupled between a third intermediate node between the third and the fourth N-type transistors, and the output node; and

a ninth transistor coupled between a fourth intermediate node between the third and the fourth P-type transistors, and the output node.

12. A semiconductor device comprising:

a memory array provided with electrically rewritable nonvolatile memory cells arranged in a matrix,

wherein the memory array comprises;

a plurality of word lines each corresponding to a row of the memory array, and is divided into a plurality of blocks every plurality of rows of the memory array,

wherein the semiconductor device further comprises;

a driver circuit operable to drive the word lines,

wherein the driver circuit comprises;

a plurality of driver groups respectively corresponding to the blocks,

wherein each of the driver groups comprises;

a first power supply line on a low potential side;

a second power supply line on a high potential side; and

a plurality of drivers operable to drive respectively the word lines provided in the corresponding block,

wherein the semiconductor device further comprises;

a first decode circuit operable to supply a first power supply potential according to the operation mode to each of the first power supply lines, based on a plurality of first predecode signals,

wherein the first decode circuit comprises;

a plurality of first logic gates each operable to invert a logical level of the corresponding first predecode signal according to the operation mode;

a plurality of first level shifters each operable to convert one of the corresponding first predecode signal and its inverted signal into a step-up signal of a voltage level according to the operation mode; and

a plurality of first logic circuits each operable to perform a logical operation of the corresponding step-up signals among the step-up signals respectively outputted from the first level shifters to generate the first power supply potential, and operable to supply the generated first power supply potential to the corresponding first power supply line, and

wherein each of the first logic circuits performs a different logical operation according to the operation mode.

13. The semiconductor device according to claim 12 further comprising:

a second decode circuit operable to supply a second power supply potential according to the operation mode to each of the second power supply lines, based on the first predecode signals,

wherein the second decode circuit comprises;

a plurality of second level shifters each operable to convert one of the corresponding first predecode signal and its inverted signal into a step-up signal of a voltage level according to the operation mode; and

a plurality of second logic circuits each operable to perform a logical operation of the corresponding step-up signals among the step-up signals respectively outputted from the second level shifters to generate the second power supply potential, and operable to supply the generated second power supply potential to the corresponding second power supply line, and

wherein each of the second logic circuits performs the same logical operation irrespective of the operation mode.

14. The semiconductor device according to claim 13,

wherein each of the driver of each of the driver groups receives a gate control signal common in the driver groups, and supplies the potential of one of the first power supply line and the second power supply line, to the corresponding word line according to the gate control signal,

wherein the semiconductor device further comprises:

a third decode circuit operable to supply the gate control signal of a voltage level according to the operation mode to each of the driver of each of the driver groups, based on the second predecode signals,

wherein the third decode circuit comprises;

a plurality of second logic gates each operable to invert a logical level of the corresponding second predecode signal according to the operation mode;

a plurality of third level shifters each operable to convert one of the corresponding second predecode signal and its inverted signal into a step-up signal of a voltage level according to the operation mode; and

a plurality of third logic circuits each operable to perform a logical operation of the corresponding step-up signals among the step-up signals respectively outputted from the third level shifters to generate the gate control signal, and operable to supply the generated gate control signal to the corresponding driver, and

wherein each of the third logic circuits performs a different logical operation according to the operation mode.