Memory System and Method for Reducing Read Disturb Errors

• US 20160225461A1
• Filed: 03/31/2015
• Published: 08/04/2016
• Est. Priority Date: 01/30/2015
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Tuers, Daniel E., Manohar, Abhijeet, Thomas, Nicholas, Hsu, Jonathan
• Granted Patent: US 10,014,060 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step

Abstract

A memory system and method for reducing read disturb errors are disclosed. In one embodiment, a memory system is provided comprising a plurality of blocks of memory and a controller. The controller is configured to detect a read disturb error in a block, identify data that caused the read disturb error, and move the data that caused the read disturb error to a block with a higher read endurance. This can be done by assigning read counters to blocks to determine frequently-read data, and storing that data in a separate block until it is less frequently read and will likely not cause additional read disturb errors.

Claims

1. A method for reducing read disturb errors, the method comprising:

performing the following in a memory system comprising a plurality of blocks of memory, wherein the blocks comprise level one, level two, and level three blocks;

detecting a read disturb error in a level one block;

moving data stored in the level one block to a level two block;

monitoring read accesses to the level two block to determine what data in the level two block is frequently read;

moving the data that was determined to be frequently read from the level two block to a level three block;

monitoring read accesses to the data in the level three block to determine if the data in the level three block is read less frequently; and

in response to determining that the data in the level three block is read less frequently, moving the data from the level three block to a level one block.

2. The method of claim 1, wherein the read disturb error is detected in the level one block using a read counter.

3. The method of claim 1, wherein the read disturb error is detected in the level one block using a read-patrol technique.

4. The method of claim 1, wherein the read disturb error is detected in the level one block by reading neighboring word lines when reading a word line.

5. The method of claim 1, wherein the read accesses to the level two block are monitored with read counters.

6. The method of claim 1, wherein the read accesses to the level three block are monitored with read counters.

7. The method of claim 1, wherein the level three block has a higher read endurance than the level one block.

8. The method of claim 7, wherein the level one block comprises MLC memory cells, and wherein the level three block comprises SLC memory cells.

9. The method of claim 7, wherein the level one block comprises non-volatile memory, and wherein the level three block comprises volatile memory.

10. The method of claim 7, wherein the level three block stores dummy data in word lines surrounding the word lines that store the data.

11. The method of claim 1, wherein the memory is a three-dimensional memory.

12. The method of claim 1, wherein the memory system is embedded in a host.

13. The method of claim 1, wherein the memory system is removably connected to a host.

14. A memory system comprising:

a memory comprising a plurality of blocks; and

a controller in communication with the memory, wherein the controller is configured to;

determine that there is a read disturb error in a block;

identify data that caused the read disturb error; and

relocate the data that caused the read disturb error to a block with a higher read endurance.

15. The memory system of claim 14, wherein the controller is further configured to relocate the data to a block with a lower read endurance after the data is determined to be less likely to cause a read disturb error when read.

16. The memory system of claim 14, wherein the read disturb error is determined using a read counter.

17. The memory system of claim 14, wherein the read disturb error is determined using a read-patrol technique.

18. The memory system of claim 14, wherein the read disturb error is determined by reading neighboring word lines when reading a word line.

19. The memory system of claim 14, wherein the controller is configured to identify data in the block that is causing the read disturb error using read counters.

20. The memory system of claim 14, wherein the block with the higher read endurance comprises SLC memory cells, and wherein the block in which the read disturb error was determined comprises MLC memory cells.

21. The memory system of claim 14, wherein the block with the higher read endurance comprises volatile memory, and wherein the block in which the read disturb error was determined comprises non-volatile memory.

22. The memory system of claim 14, wherein the block with the higher read endurance stores dummy data in word lines surrounding the word lines that store the data.

23. The memory system of claim 14, wherein the memory is a three-dimensional memory.

24. The memory system of claim 14, wherein the memory system is embedded in a host.

25. The memory system of claim 14, wherein the memory system is removably connected to a host.

26. A memory system comprising:

a memory comprising a plurality of blocks;

a plurality of read counters; and

a read disturb module in communication with the memory and the plurality of read counters, wherein the read disturb module is configured to;

sense a read disturb error in a first block;

copy data from the first block to a second block;

assign read counters to the second block to identify hot read data;

copy the hot read data from the second block to a third block;

assign read counters to the third block to determine when the hot read data becomes cold read data; and

copy the cold read data from the third block to another block.

27. The memory system of claim 26, wherein the read disturb module is configured to sense read disturb errors using a read counter.

28. The memory system of claim 26, wherein the read disturb module is configured to sense read disturb errors using a read-patrol technique.

29. The memory system of claim 26, wherein the read disturb module is configured to sense read disturb errors by reading neighboring word lines when reading a word line.

30. The memory system of claim 26, wherein the third block has a higher read endurance than the first block.

31. The memory system of claim 26, wherein the first block comprises MLC memory cells, and wherein the third block comprises SLC memory cells.

32. The memory system of claim 26, wherein the first block comprises non-volatile memory, and wherein the third block comprises volatile memory.

33. The memory system of claim 26, wherein the third block stores dummy data in word lines surrounding the word lines that store the data.

34. The memory system of claim 26, wherein the memory is a three-dimensional memory.

35. The memory system of claim 26, wherein the memory system is embedded in a host.

36. The memory system of claim 26, wherein the memory system is removably connected to a host.