POWER FET WITH A RESONANT TRANSISTOR GATE

• US 20160225759A1
• Filed: 09/29/2015
• Published: 08/04/2016
• Est. Priority Date: 08/23/2010
• Status: Active Grant

• Current Assignee: L. Pierre De Rochemont
• Original Assignee: L. Pierre De Rochemont
• Inventors: de Rochemont, L. Pierre
• Granted Patent: US 9,881,915 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: H01L 2223/6627 Waveguides, e.g. microstrip line, strip line, coplanar line
• CPC Class Codes: H01L 2223/6661 for passive devices
• CPC Class Codes: H01L 23/5222 Capacitive arrangements or effects of, or between wiring layers other capacitive arrangements H01L23/642
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 23/64 Impedance arrangements
• CPC Class Codes: H01L 23/642 Capacitive arrangements H01L23/49589, H01L23/645, H01L23/647, H01L23/66 take precedence; capacitive effects between wiring layers on the semiconductor body H01L23/5222
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 25/16 the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 28/10 Inductors
• CPC Class Codes: H01L 28/20 Resistors
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/43 characterised by the materials of which they are formed
• CPC Class Codes: H01L 29/435 : Resistive materials for field effect devices, e.g. resistive gate for MOSFET or MESFET
• CPC Class Codes: H01L 29/7395 : Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/78 : with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7803 : structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7831 : with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor FET provides a resonant gate and source and drain electrodes, wherein the resonant gate is electromagnetically resonant at one or more predetermined frequencies.

Claims

1. A semiconductor FET, comprising a resonant gate and source and drain electrodes, wherein the resonant gate is electromagnetically resonant at one or more predetermined frequencies.

2. The FET of claim 1, wherein the resonant gate includes integrally constructed reactive components connected in series or parallel with resonant gate segments.

3. The FET of claim 2, wherein the reactive components include ceramic dielectric material.

4. The FET of claim 3, wherein the dielectric material has dielectric properties that vary ≦

±

1% over temperatures in the range of −

40°

C. to +120°

C.

5. The FET of claim 1, further comprising a plurality of embedded capacitive circuit elements electrically connected in series with one or more resonant gate segments to form a lumped capacitance that reduces overall input capacitance of the resonant gate.

6. The FET of claim 1, wherein the resonant gate has adjacently located segments which reactively couple to each other.

7. The FET of claim 6, further comprising dielectric material integrally constructed to affect the reactive coupling between adjacently located segments of the resonant gate.

8. The FET of claim 1, wherein the resonant gate forms an elongated resonant transmission line.

9. The FET of claim 8, further comprising reactive and resistive components integrally constructed within the resonant gate to form the elongated resonant transmission line in combination with segments of the resonant gate, which elongated transmission line is resonant at one or more predetermined frequencies.

10. The FET of claim 9, wherein the resistive component is located to terminate the resonant transmission line.

11. The FET of claim 9, wherein one or more resistive components within the resonant gate are adapted to control bandwidth of the resonant gate.

12. The FET of claim 1, wherein gate electrode has a gate width to gate length ratio≧

100.

13. The FET of claim 1, wherein the gate width to gate length ratio is greater than either one thousand, ten thousand, one hundred thousand or one million to one.

14. The FET of claim 1, wherein the resonant gate is constructed to have a serpentine path.

15. The FET of claim 13, wherein the serpentine path induces electromagnetic coupling between adjacent segments of the resonant gate.

16. The FET of claim 14, wherein the serpentine path obeys a fractal geometry.

17. The FET of claim 1, further comprising a power management module integrated in a monolithic structure with the FET.

18. The FET of claim 17, wherein the integrated FET and monolithic power management module are formed on silicon, silicon germanium, or a III-V compound semiconductor.

19. The FET of claim 1, wherein the FET is a DDMOS, superjunction or IGBT vertical FET, or a surface FET.

20. A power management module, comprising the FET of claim 1.

21. (canceled)

22. (canceled)