MRAM WITH METAL-INSULATOR-TRANSITION MATERIAL

• US 20160225818A1
• Filed: 02/01/2016
• Published: 08/04/2016
• Est. Priority Date: 02/03/2015
• Status: Active Grant

• Current Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Original Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Inventors: TOH, Eng Huat, NAIK, Vinayak Bharat, WANG, Chenchen Jacob, QUEK, Kiok Boone Elgin
• Granted Patent: US 10,134,459 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 11/1657 Word-line or row circuits
• CPC Class Codes: G11C 11/1659 Cell access
• CPC Class Codes: G11C 11/1673 Reading or sensing circuits or methods
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: H10B 61/22 of the field-effect transistor [FET] type
• CPC Class Codes: H10N 50/01 Manufacture or treatment
• CPC Class Codes: H10N 50/10 Magnetoresistive devices
• CPC Class Codes: H10N 50/80 Constructional details

Abstract

Memory cells and methods for forming a memory cell are disclosed. The memory cell includes a first selector having a first gate coupled to a first word line (WL) and first and second source/drain (S/D) regions, and a second selector having a second gate coupled to a second WL and first and second S/D regions. The second S/D regions of the first and the second selectors are a common S/D region. The first and the second WLs are a common WL and the second S/D regions of the first and second selectors are coupled to a source line (SL). The memory cell includes a storage element which includes a magnetic tunnel junction (MTJ) element coupled with a bit line (BL) and the first and the second selectors, and a voltage control switch which includes a metal-insulator-transition (MIT) material coupled with the first selector.

Claims

1. A memory cell comprising:

a first selector having a first gate coupled to a first word line (WL) and first and second source/drain (S/D) regions;

a second selector having a second gate coupled to a second WL and first and second S/D regions, wherein the second S/D regions of the first and the second selectors are a common S/D region, the first and the second WLs are a common WL and the second S/D regions of the first and second selectors are coupled to a source line (SL);

a storage element which comprises a magnetic tunnel junction (MTJ) element coupled with a bit line (BL) and the first and the second selectors; and

a voltage control switch which comprises a metal-insulator-transition (MIT) material coupled with the first selector.

2. The memory cell of claim 1 wherein the MIT material comprises a phase transition characteristic such that it is in conductive state when subject to high voltage and in insulating state when subject to low voltage.

3. The memory cell of claim 2 wherein the MIT material is coupled with the first S/D region of the first selector.

4. The memory cell of claim 3 wherein the MIT material is disposed between the SL and the first S/D region of the first selector.

5. The memory cell of claim 4 wherein the MIT material is disposed in a metal level, wherein the metal level is the same metal level where the SL is disposed and the MIT material is disposed below the SL.

6. The memory cell of claim 2 wherein the MIT material is coupled with the first gate of the first selector.

7. The memory cell of claim 6 wherein the MIT material is electrically coupled in series between the WL and the first gate of the first selector.

8. The memory cell of claim 7 wherein the first gate of the first selector comprises a first gate electrode and a first gate dielectric, wherein the MIT material is disposed in between the first gate electrode and first gate dielectric.

9. The memory cell of claim 1 wherein the first and the second selectors are coupled electrically in parallel.

10. The memory cell of claim 1 wherein the MTJ element is coupled with the second S/D regions of the first and the second selectors.

11. The memory cell of claim 1 wherein the MTJ element comprises:

a top electrode;

a bottom electrode; and

a MTJ stack in between the top and bottom electrodes, wherein the MTJ stack comprises a magnetically free layer, a magnetically fixed layer and a tunnel barrier layer between the free and fixed layers.

12. A method of operating a memory cell comprising:

providing a memory cell comprising

a first selector having a first gate coupled to a first word line (WL) and first and second source/drain (S/D) regions,

a second selector having a second gate coupled to a second WL and first and second S/D regions, wherein the second S/D regions of the first and the second selectors are a common S/D region, the first and the second WLs are a common WL and the second S/D regions of the first and second selectors are coupled to a source line (SL),

a storage element which comprises a magnetic tunnel junction (MTJ) element coupled with a bit line (BL) and the first and the second selectors, and

a voltage control switch which comprises a metal-insulator-transition (MIT) material coupled with the first selector; and

performing a read operation or write operation with the memory cell, wherein

when a write operation is performed or high voltage is applied to the common WL, the MIT material is in conductive state and the first selector is turned ON, and

when a read operation is performed or low voltage is applied to the common WL, the MIT material is in insulating state and the first selector is turned OFF while the WL conducts appropriate current to the second selector such that the second selector is turned ON.

13. A method of forming a memory cell comprising:

providing a substrate defined with a memory cell region;

forming a first selector on the substrate, wherein the first selector comprises a first gate and first and second source/drain (S/D) regions;

forming a second selector on the substrate, wherein the second selector comprises a second gate and first and second S/D regions, wherein the second S/D regions of the first and second selectors are a common second S/D region and the first and second gates are coupled to a common wordline (WL);

forming a voltage control switch which comprises a metal-insulator-transition (MIT) material coupled with the first selector;

forming a storage element which comprises a magnetic tunnel junction (MTJ) element in a storage dielectric layer over the first and second selectors;

forming an upper metal level which comprises a bit line (BL) over the storage dielectric layer; and

coupling the MTJ element between the BL and the common second S/D region of the first and second selectors.

14. The method of claim 13 wherein forming the first and second selectors comprises:

forming gate layers which comprise a gate dielectric layer and a gate electrode layer over the substrate; and

patterning the gate layers to form the first and second gates and wherein the first and second gates are interconnected through a patterned gate layout to form the common WL.

15. The method of claim 13 wherein the MIT material comprises a phase transition characteristic such that it is in conductive state when subject to high voltage and in insulating state when subject to low voltage.

16. The method of claim 15 wherein forming the voltage control switch comprises forming the MIT material over the first S/D region of the first selector.

17. The method of claim 16 comprising:

forming a pre-metal dielectric (PMD) layer over the first and second selectors;

forming metal lines over the PMD layer, wherein the metal lines comprise a source line SL; and

coupling the first S/D regions of the first and second selectors to the SL.

18. The method of claim 17 wherein the MIT material is formed between the SL and the first S/D region of the first selector.

19. The method of claim 15 wherein:

forming the voltage control switch comprises forming a MIT layer over the gate dielectric layer;

patterning the MIT material prior to forming the gate electrode layer; and

patterning the gate layers to form the first and second gates, wherein the patterned MIT material is formed below the patterned gate electrode of the first gate.

20. The method of claim 13 wherein forming the storage element comprises:

forming a top electrode;

forming a bottom electrode; and

forming a MTJ stack in between the top and bottom electrodes, wherein the MTJ stack comprises a magnetically free layer, a magnetically fixed layer and a tunnel barrier layer between the free and fixed layers.