SEMICONDUCTOR DEVICE WITH TUNABLE WORK FUNCTION

• US 20160225871A1
• Filed: 01/29/2015
• Published: 08/04/2016
• Est. Priority Date: 01/29/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: CHENG, Chung-Liang, CHEN, Wei-Jen, CHEN, Yen-Yu, ZHANG, Wei
• Granted Patent: US 9,548,372 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/823857 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence

Abstract

The metal-oxide semiconductor structure includes a substrate, a gate dielectric multi-layer, an etch stop layer, a work function metallic layer, a barrier layer and a silicide layer. The substrate has a trench. The gate dielectric multi-layer overlies the trench, in which the gate dielectric multi-layer includes a high-k capping layer with a fluorine concentration substantially in a range from 1 at % to 10 at %. The etch stop layer is disposed on the gate dielectric multi-layer. The work function metallic layer is disposed on the etch stop layer. The barrier layer is disposed on the work function metallic layer. The silicide layer is disposed on the barrier layer.

Claims

1. A metal-oxide semiconductor structure, comprising:

a substrate with a trench;

a gate dielectric multi-layer overlying the trench, wherein the gate dielectric multi-layer includes a high-k capping layer with a fluorine concentration substantially in a range from 1 at % to 10 at %;

an etch stop layer disposed on the gate dielectric multi-layer;

a work function metallic layer disposed on the etch stop layer;

a barrier layer disposed on the work function metallic layer; and

a silicide layer disposed on the barrier layer.

2. The metal-oxide semiconductor structure of claim 1, wherein the work function metallic layer is a n-type work function metallic layer.

3. The metal-oxide semiconductor structure of claim 1, wherein the work function metallic layer includes a n-type work function metallic layer and a p-type work function metallic layer, wherein the p-type work function metallic layer is disposed on the etch stop layer, and the n-type work function metallic layer is disposed on the p-type work function metallic layer.

4. The metal-oxide semiconductor structure of claim 1, wherein the fluorine concentration is substantially in a range from 1 at % to 4 at %.

5. A semiconductor device, comprising:

a substrate with a first trench and a second trench;

a first metal-oxide semiconductor structure on the substrate, comprising;

a first gate dielectric multi-layer overlying the first trench, wherein the first gate dielectric multi-layer includes a first high-k capping layer with a first fluorine concentration substantially in a range from 1 at % to 10 at %;

a first etch stop layer disposed on the first gate dielectric multi-layer;

a first work function metallic layer disposed on the first etch stop layer;

a first barrier layer disposed on the first work function metallic layer; and

a first silicide layer disposed on the first barrier layer; and

a second metal-oxide semiconductor structure on the substrate, the second metal-oxide semiconductor structure is adjacent to the first metal-oxide semiconductor structure, wherein the second metal-oxide semiconductor structure comprises;

a second gate dielectric multi-layer overlying the second trench;

a second etch stop layer disposed on the second gate dielectric multi-layer;

a second work function metallic layer disposed on the second etch stop layer;

a second barrier layer disposed on the second work function metallic layer; and

a second silicide layer disposed on the second barrier layer.

6. The semiconductor device of claim 5, wherein the first work function metallic layer includes a n-type work function metallic layer and a p-type work function metallic layer, wherein the p-type work function metallic layer is disposed on the etch stop layer and the n-type work function metallic layer is disposed on the p-type work function metallic layer.

7. The semiconductor device of claim 5, wherein the second work function metallic layer is a n-type work function metallic layer.

8. The semiconductor device of claim 7, wherein the second work function metallic layer includes a second high-k capping layer with a second fluorine concentration substantially in a range from 1 at % to 10 at %.

9. The semiconductor device of claim 8, wherein the second fluorine concentration is in a range from 1 at % to 4 at %.

10. The semiconductor device of claim 5, wherein the first fluorine concentration is in a range from 1 at % to 4 at %.

11. The semiconductor device of claim 5, wherein the first metal-oxide semiconductor structure is a p-type metal-oxide semiconductor structure and the second metal-oxide semiconductor structure is a n-type metal-oxide semiconductor structure.

12. A method for fabricating a semiconductor device, comprising:

providing a substrate with a first region and a second region, wherein a first dummy poly gate and a second dummy poly gate are formed in the first region and the second region respectively;

removing the first dummy poly gate and the second dummy poly gate to form a first trench and a second trench;

forming a gate dielectric multi-layer on the first region and the second region, wherein the gate dielectric multi-layer includes a high-k capping layer;

forming an etch stop layer on the gate dielectric multi-layer;

forming a sacrificial layer on the etch stop layer, wherein the sacrificial layer is formed from titanium nitride and has a predetermined crystalline orientation ratio of [200] to [111];

performing a thermal treatment using tungsten hexafluoride on the sacrificial layer on the first region, thereby enabling the high-k capping layer on the first region to have a fluorine concentration substantially in a range from 1 at % to 10 at %;

removing the sacrificial layer to expose the etch stop layer;

forming a first-type work function metallic layer on the etch stop layer on the first region;

forming a second-type work function metallic layer on the etch stop layer on the second region and on the first-type work function metallic layer;

forming a barrier layer on the second-type work function metallic layer; and

forming a silicide layer on the barrier layer.

13. The method of claim 12, wherein after the operation of forming the silicide layer on the barrier layer, the method further comprises performing a chemical mechanical polishing operation on the first region and the second region.

14. The method of claim 12, wherein the operation of performing the thermal treatment on the sacrificial layer gate on the first region further comprises:

forming a dielectric material on the sacrificial layer;

patterning the dielectric material to expose the sacrificial layer on the first region;

performing the tungsten hexafluoride thermal treatment on the sacrificial layer on the first region and the dielectric material on the second region; and

removing the dielectric material on the second region.

15. The method of claim 12, wherein the operation of forming the first-type work function metallic layer on the etch stop layer on the first region further comprises:

forming the first-type work function metallic layer on the etch stop layer;

forming a dielectric material on the first-type work function metallic layer;

patterning the dielectric material to expose the first-type work function metallic layer on the second region;

removing the first-type work function metallic layer on the second region; and

removing the dielectric material on the first region.

16. The method of claim 12, wherein the operation of forming the sacrificial layer on the etch stop layer further comprises forming the sacrificial layer formed from titanium nitride on the etch stop layer.

17. The method of claim 12, wherein the operation of forming the first-type work function metallic layer on the etch stop layer on the first region further comprises forming a p-type work function metallic layer on the etch stop layer on the first region.

18. The method of claim 12, wherein the operation of forming the second-type work function metallic layer on the etch stop layer on the second region and on the first-type work function metallic layer further comprises forming a n-type work function metallic layer on the etch stop layer on the second region and on the first-type work function metallic layer.

19. The method of claim 12, wherein the operation of performing the tungsten hexafluoride thermal treatment further comprises performing the tungsten hexafluoride thermal treatment with a process temperature substantially in a range from 300°

C. to 600°

C.

20. The method of claim 12, wherein the operation of forming the sacrificial layer on the etch stop layer further comprises forming the sacrificial layer having the predetermined crystal structure with the predetermined crystalline orientation ratio substantially in a range from 0.66 to 0.92.