Metal oxynitride transistor devices

• US 20160225915A1
• Filed: 01/30/2015
• Published: 08/04/2016
• Est. Priority Date: 01/30/2015
• Status: Abandoned Application

• Current Assignee: Andy Shih, Chunong Qiu, Cindy X. Qiu, Ishiang Shih, Julia Qiu, Yi-Chi Shih
• Original Assignee: Andy Shih, Chunong Qiu, Cindy X. Qiu, Ishiang Shih, Julia Qiu, Yi-Chi Shih
• Inventors: Qiu, Cindy X., Shih, Andy, Shih, Yi-Chi, Shih, Ishiang, Qiu, Chunong, Qiu, Julia
• Application Number:
  US14/544,652
• Publication Number:
  US 20160225915A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/24 including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22 including organic materials H10K99/00
• CPC Class Codes: H01L 29/423 not carrying the current to be rectified, amplified or switched
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/78609 for preventing leakage current H01L29/78618 takes precedence
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Transistors with a first metal oxynitride channel layer and a second metal oxynitride barrier layer are provided. The first metal oxynitride channel layer is lightly doped or without intentional doping to achieve high carrier mobility. Impurity atoms are introduced into the second metal oxynitride barrier layer and the donated carriers migrate or drift into the first metal oxynitride channel layer to effect high mobility conduction between source and drain.

Claims

1. A metal oxynitride transistor for forming an electronic circuit, comprises:

a substrate;

a first metal oxynitride channel layer with a first metal oxynitride energy band gap, a first metal oxynitride electron affinity, a first metal oxynitride donor density and a first metal oxynitride channel layer thickness;

a second metal oxynitride bather layer having a second metal oxynitride energy band gap, a second metal oxynitride electron affinity, a second metal oxynitride donor density and a second metal oxynitride barrier layer thickness to provide electrons, said second metal oxynitride donor density is higher than said first metal oxynitride donor density;

a source layer with a source layer thickness;

a drain layer with a drain layer thickness; and

at least a first gate layer having a first gate layer length and a first gate layer thickness, wherein said first metal oxynitride energy band gap, said first metal oxynitride electron affinity, said second metal oxynitride energy band gap and said second metal oxynitride electron affinity are selected to form an conduction energy band step between said second metal oxynitride bather layer and said first metal oxynitride channel layer so that free electrons donated in said second metal oxynitride barrier layer will be separated from ionized donors and move into said first metal oxynitride channel layer to achieve high electron mobility for conduction between said source layer and said drain layer.

2. The metal oxynitride transistor for forming the electronic circuit as defined in claim 1, wherein metals for forming said first metal oxynitride channel layer are selected from a group including:

In, Zn, Sn, Ga, Ba, La, B, Al, Mg, Ca, Sr, Ba and their mixtures.

3. The metal oxynitride transistor for forming the electronic circuit as defined in claim 1, wherein metals for forming said second metal oxynitride bather layer are selected from a group including:

In, Zn, Sn, Ga, Ba, La, B, Al, Mg, Ca, Sr, Ba and their mixtures.

4. The metal oxynitride transistor for forming the electronic circuit as defined in claim 1, wherein doping impurity atoms are introduced in said second metal oxynitride bather layer to donate electrons and no intentional doping impurity atoms are introduced in said first metal oxynitride channel layer, said electrons donated by said doping impurity atoms in said second metal oxynitride barrier layer drift or migrate to said first metal oxynitride channel layer.

5. The metal oxynitride transistor for forming the electronic circuit as defined in claim 1, wherein said first metal oxynitride energy band gap is smaller than said second metal oxynitride energy band gap for forming a conduction energy band step between said first metal oxynitride channel layer and said second metal oxynitride barrier layer to facilitate separation of free charges from immobile ionized donors in said second metal oxynitride barrier layer and to increase mobility of said free charges.

6. The metal oxynitride transistor for forming the electronic circuit as defined in claim 1, wherein said first metal oxynitride energy band gap is similar to said second metal oxynitride energy band gap and said first metal oxynitride electron affinity is greater than said second metal oxynitride electron affinity for forming a conduction energy band step between said first metal oxynitride channel layer and said second metal oxynitride bather layer to facilitate charge separation and to increase mobility.

7. The metal oxynitride transistor for forming the electronic circuit as defined in claim 1, wherein said first metal oxynitride channel layer thickness is selected to be in a range of 5 nm to 1000 nm and more preferably in a range of 10 nm to 400 nm.

8. The metal oxynitride transistor for forming the electronic circuit as defined in claim 1, wherein said second metal oxynitride bather layer thickness is selected to be in a range of 3 nm to 200 nm and more preferably in a range of 5 nm to 40 nm.

9. The metal oxynitride transistor for forming the electronic circuit as defined in claim 1, further comprising a gate insulating layer having a gate insulating layer thickness deposited between said second metal oxynitride layer and said first gate layer, forming an MIS structure to reduce leakage currents from said first gate layer and for modulating charges in said first metal oxynitride layer, wherein materials of said gate insulating layer may be selected from a group including silicon dioxide, silicon nitride, aluminum oxide, aluminum nitride, hafnium oxide, gallium oxide, barium strontium titanite and their mixtures.

10. The metal oxynitride transistor for forming the electronic circuit as defined in claim 1, wherein material of said first gate layer is selected from a group of large work function metals including:

Ni, W, Mo, Ta, Pt, Cu, Al, Au and their alloys to form a rectifying contact between said first gate layer and said second metal oxynitride bather layer.

11. The metal oxynitride transistor for forming the electronic circuit as defined in claim 1, further comprising a second gate layer having a second gate length and a second gate layer thickness deposited on said first gate layer, material of said second gate layer is selected from a high conductivity materials including:

Au, Al, Cu, Ag and their combinations to reduce unwanted series resistance of said first gate layer and said second gate layer.

12. The metal oxynitride transistor for forming the electronic circuit as defined in claim 1, further comprising a buffer layer having a buffer layer thickness deposited on said substrate to reduce unwanted defect density in said first metal oxynitride channel layer.

13. The metal oxynitride transistor for forming the electronic circuit as defined in claim 1, further comprising a carrier blocking layer having a carrier blocking layer energy band gap and a carrier blocking layer thickness situated between said substrate and said first metal oxynitride channel layer to reduce defects and to confine free electrons in said first metal oxynitride channel layer, said carrier blocking layer thickness is selected to be in a range of 20 nm˜

2,000 nm, wherein materials of said carrier blocking layer are selected so that an energy step is formed between conduction band edges of said carrier blocking layer and said first metal oxynitride channel layer.

14. The metal oxynitride transistor for forming the electronic circuit as defined in claim 1, further comprising a passivation layer having a passivation layer thickness covering a portion of said source layer and a portion of said drain layer, said first gate layer and exposed regions of said second metal oxynitride bather layer, wherein materials of said passivation layer are selected from a group including:

silicon dioxide, silicon nitride, hafnium oxide and their combinations.

15. The metal oxynitride transistor for forming the electronic circuit as defined in claim 1, wherein materials of said source and said drain are selected to form a non-rectifying contact with low resistance between said source and drain and said first metal oxynitride channel layer.

16. The metal oxynitride transistor for forming the electronic circuit as defined in claim 1, wherein said substrate is selected from group of glass plates, plastic sheets, alumina plates, aluminum nitride plates, stainless steel sheets, silicon wafer, Si and GaAs substrates with prefabricated digital and analog microelectronic circuits.

17. The metal oxynitride transistor for forming the electronic circuit as defined in claim 1, further comprising a spacer layer having a spacer layer thickness situated between said first metal oxynitride channel layer and said second metal oxynitride barrier layer to reduce unwanted coulomb interactions of free electrons in said first metal oxynitride channel layer, said spacer layer thickness is selected to be in a range of:

1 nm˜

10 nm, material of said spacer layer may be preferably selected to be the same as that of said second metal oxynitride bather layer and no intentional doping is introduced in said spacer layer.

18. The metal oxynitride transistor for forming the electronic circuit as defined in claim 1, further comprises a impurity doping layer with an impurity doping layer thickness deposited between said first metal oxynitride channel layer and said second metal oxynitride barrier layer to supply charge carriers for conduction in said first metal oxynitride channel layer, whereas no intentional impurity doping is introduced in said second metal oxynitride bather layer to reduce unwanted gate leakage and increase gate breakdown voltage.