PHASE DETECTOR AND DIGITAL PLL CIRCUIT USING THE SAME

• US 20160226656A1
• Filed: 08/20/2015
• Published: 08/04/2016
• Est. Priority Date: 01/29/2015
• Status: Abandoned Application

• Current Assignee: Semiconductor Technology Academic Research Center
• Original Assignee: Semiconductor Technology Academic Research Center
• Inventors: OKADA, Kenichi
• Application Number:
  US14/831,111
• Publication Number:
  US 20160226656A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/22 using more than one loop
• CPC Class Codes: H03L 7/23 with pulse counters or frequency dividers

Abstract

According to one embodiment, a phase detector includes an amplifier and an analog-to-digital converter. The amplifier amplifies a voltage of a signal which is output from a digitally-controlled oscillator and is held based on a reference signal. The analog-to-digital converter converts the voltage amplified by the amplifier into a digital signal, based on the reference signal.

Claims

1. A phase detector, comprising:

an amplifier configured to amplify a voltage of a signal which is output from a digitally-controlled oscillator and is held based on a reference signal; and

an analog-to-digital converter configured to convert the voltage amplified by the amplifier into a digital signal, based on the reference signal.

2. The phase detector according to claim 1, further comprising:

a sample-and-hold circuit configured to hold the voltage of the signal output from the digitally-controlled oscillator, based on the reference signal.

3. The phase detector according to claim 1, wherein

the amplifier is a variable gain amplifier, and a gain of the variable gain amplifier is controlled based on an output signal of the analog-to-digital converter.

4. The phase detector according to claim 2, wherein

the sample-and-hold circuit comprises:

a booster circuit configured to boost the reference signal;

a transistor configured to control by an output signal of the booster circuit, and to pass through a voltage supplied from the digitally-controlled oscillator; and

a capacitor configured to charge with a voltage supplied from the transistor.

5. A digital phase-locked loop circuit, comprising:

a digitally-controlled oscillator configured to oscillate a signal, based on a control signal;

an analog-to-digital converter configured to convert a voltage of a signal which is output from the digitally-controlled oscillator and is held based on a reference signal, into a digital signal; and

a digital filter configured to produce the control signal to control the digitally-controlled oscillator, from an output signal of the analog-to-digital converter.

6. The circuit according to claim 5, further comprising

a sample-and-hold circuit configured to hold the voltage of the signal output from the digitally-controlled oscillator, based on the reference signal.

7. The circuit according to claim 5, further comprising

an amplifier configured to amplify the held voltage.

8. The circuit according to claim 7, wherein

the amplifier is a variable gain amplifier, and a gain of the variable gain amplifier is controlled based on the output signal of the analog-to-digital converter.

9. The circuit according to claim 5, further comprising

a digital-to-time converter to which the output signal of the digitally-controlled oscillator is supplied, wherein the digital-to-time converter gives a delay to the output signal of the digitally-controlled oscillator.

10. The circuit according to claim 5, further comprising

a digital-to-time converter configured to give a delay to the reference signal.

11. The circuit according to claim 5, further comprising

a waveform shaping circuit configured to shape the output signal of the digitally-controlled oscillator.

12. The circuit according to claim 5, further comprising

a circuit to which the output signal of the digitally-controlled oscillator is supplied, wherein the circuit gives a voltage offset to the output signal of the digitally-controlled oscillator.

13. The circuit according to claim 5, wherein

the digitally-controlled oscillator is an LC-type digitally-controlled oscillator.

14. The circuit according to claim 5, wherein

the digitally-controlled oscillator is a ring-type digitally-controlled oscillator.

15. The circuit according to claim 6, wherein

the sample-and-hold circuit comprises:

a booster circuit configured to boost the reference signal;

a transistor configured to control by an output signal of the booster circuit, and to pass through a voltage supplied from the digitally-controlled oscillator; and

a capacitor configured to charge with a voltage supplied from the transistor.

16. A digital phase-locked loop circuit, comprising:

a digitally-controlled oscillator configured to oscillate a signal, based on a control signal;

a sample-and-hold circuit configured to hold a voltage of a signal output from the digitally-controlled oscillator, based on the reference signal;

an amplifier configured to amplify the voltage held by the sample-and-hold circuit;

an analog-to-digital converter configured to convert the voltage amplified by the amplifier into a digital signal; and

a digital filter configured to produce the control signal to control the digitally-controlled oscillator, from an output signal of the analog-to-digital converter.

17. The circuit according to claim 16, wherein

the amplifier is a variable gain amplifier, and a gain of the variable gain amplifier is controlled based on the output signal of the analog-to-digital converter.

18. The circuit according to claim 16, further comprising

a digital-to-time converter to which the output signal of the digitally-controlled oscillator is supplied, wherein tie digital-to-time converter gives a delay to the output signal of the digitally-controlled oscillator.

19. The circuit according to claim 16, further comprising

a digital-to-time converter configured to give a delay to the output signal of the digitally-controlled oscillator.

20. The circuit according to claim 16, further comprising

a waveform shaping circuit configured to shape the output signal of the digitally-controlled oscillator.