LOW DROPOUT REGULATOR WITH HYSTERETIC CONTROL

• US 20160231761A1
• Filed: 04/19/2016
• Published: 08/11/2016
• Est. Priority Date: 09/25/2012
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Jain, Rinkle, Shih, Yi-Chun, Vaidya, Vaibhav
• Application Number:
  US15/133,177
• Publication Number:
  US 20160231761A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G05F 1/56 using semiconductor devices in series with the load as final control devices G05F1/461 takes precedence
• CPC Class Codes: G05F 1/565 sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor G05F1/563 takes precedence

Abstract

Described is an apparatus comprising: an output stage having an input supply node to receive an input power supply and an output node to provide an output supply to a load; an amplifier to control current strength of the output stage according to the output supply and a reference voltage; and a hysteresis unit to monitor the output supply and operable to control the current strength of the output stage according to a voltage level of the output supply. Described is another apparatus which comprises: a plurality of charge pumps to adjust current strength of the output stage; and a logic unit to monitor the output supply and operable to control the plurality of charge pumps according to a voltage level of the output supply and one or more reference voltages.

Claims

1. An apparatus comprising:

an output stage comprising

an input supply node to receive an input power supply, and

an output supply node to provide an output supply based on the input power supply to a load;

an amplifier to output a control signal to control the output stage according to the output supply and a first reference voltage;

and

a hysteresis unit having an input and an output, wherein the hysteresis unit input is coupled to the output supply node, and wherein the hysteresis unit output is coupled to the amplifier output to adjust the control signal according to the output supply and a second reference voltage.

2. The apparatus of claim 1, wherein the output stage comprises:

a first transistor coupled to the amplifier; and

one or more second transistors operable to be selectively turned on or off by the hysteresis unit.

3. The apparatus of claim 1, wherein the second reference voltage is lower than the first reference voltage, and wherein the hysteresis unit is to adjust the control signal to increase the output supply voltage.

4. The apparatus of claim 1, wherein the second reference voltage is higher than the first reference voltage, and wherein the hysteresis unit is to adjust the control signal to decrease the output supply voltage.

5. The apparatus of claim 1, further comprising

a charge pump coupled to the output of the amplifier.

6. The apparatus of claim 1, wherein the hysteresis unit comprises:

a plurality of comparators coupled to the output supply node.

7. The apparatus of claim 1, further comprising

a bias circuit to generate a bias signal to adjust an electric current of the output stage.

8. An apparatus comprising:

an output stage comprising an input supply node to receive an input power supply, an output supply node to provide an output power supply based on the input power supply;

a plurality of charge pumps coupled to the output stage to regulate the output power supply; and

a logic unit comprising a plurality of comparators to coupled to the plurality of charge pumps to regulate a voltage level of the output supply based on a plurality of reference voltages.

9. The apparatus of claim 8, wherein the plurality of comparators comprises a first comparator coupled to a first charge pump of the plurality of charge pumps to reduce a drive strength of the output stage when the output supply is greater than a first reference voltage and a second comparator coupled to a second charge pump of the plurality of charge pumps to increase drive strength of the output stage when the output supply is less than a second reference voltage.

10. The apparatus of claim 8 further comprising

a reference generator to generate at least one of the reference voltages.

11. The apparatus of claim 8, wherein the output stage comprises a transistor having a gate terminal coupled to the plurality of charge pumps.

12. The apparatus of claim 8, wherein the plurality of reference voltages are different voltages.

13. The apparatus of claim 8, wherein the output stage is a part of a low dropout regulator embedded within a switch capacitor voltage regulator.

14. The apparatus of claim 8, wherein the logic unit comprises

a counter.

15. The apparatus of claim 8, wherein the logic unit comprises an input to receive a clock signal.

16. The apparatus of claim 8, wherein at least one of the plurality of charge pumps comprises a weighted transistor array and a weighted resistor array coupled to the output stage.

17. A system comprising:

a memory;

a processor, coupled to the memory, the processor comprising a low dropout regulator comprising;

an output stage comprising an input supply node to receive an input power supply, and an output supply node to provide an output supply to a load based on the input power supply;

an amplifier to output a control signal to control the output stage according to the output supply and a first reference voltage;

and

a hysteresis circuit having an input and an output, wherein the hysteresis circuit input is coupled to the output supply node, and wherein the hysteresis circuit output is coupled to the amplifier output to adjust the control signal according to the output supply and a second reference voltage.

18. The system of claim 17, wherein the output stage comprises:

a first transistor coupled to the amplifier; and

one or more second transistors operable to be selectively turned on or off by the hysteresis unit.

19. The system of claim 17, further comprising

a charge pump coupled to the output of the amplifier.

20. The system of claim 17, further comprising

a bias circuit to generate a bias signal to adjust an electric current of the output stage.