Integrated Circuit Having a MOM Capacitor and Method of Making Same

• US 20160233213A1
• Filed: 04/18/2016
• Published: 08/11/2016
• Est. Priority Date: 11/04/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liu, Chi-Wen, Wang, Chao-Hsiung
• Granted Patent: US 10,163,896 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 28/90 having vertical extensions
• CPC Class Codes: H01L 29/40 Electrodes ; Multistep manufacturing processes therefor
• CPC Class Codes: H01L 29/94 Metal-insulator-semiconductors, e.g. MOS
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An integrated circuit can include a MOM capacitor formed simultaneously with other devices, such as finFETs. A dielectric layer formed on a substrate has a first semiconductor fin therein and a second semiconductor fin therein. Respective top portions of the fins are removed to form respective recesses in the dielectric layer. First and second electrodes are formed in the recesses. The first and second electrodes and the interjacent dielectric layer form a MOM capacitor.

Claims

1. An integrated circuit comprising:

a capacitor, the capacitor including

a substrate;

a capacitor dielectric layer on a major surface of the substrate, the capacitor dielectric layer having a first recess and a second recess therein;

a first semiconductor fin extending from the major surface of the substrate within the first recess;

a first capacitor electrode within the first recess and atop the first semiconductor fin;

a second semiconductor fin extending from the major surface of the substrate and within the second recess; and

a second capacitor electrode within the second recess and atop the second semiconductor fin.

2. The integrated circuit of claim 1 further comprising:

a third recess in the capacitor dielectric layer;

a third semiconductor fin extending from the major surface of the substrate and within the third recess; and

a third capacitor electrode within the third recess and atop the third semiconductor fin;

wherein the first and third capacitor electrodes are electrically connected to one another.

3. The integrated circuit of claim 1 further comprising:

a liner dielectric material lining a sidewall and a bottom of at least one of the first or second recess.

4. The integrated circuit of claim 1 wherein the substrate comprises a silicon on insulator substrate.

5. The integrated circuit of claim 3 wherein the liner dielectric material comprises silicon oxide or a high-k dielectric comprising a metal Oxide.

6. The integrated circuit of claim 1 wherein the first and second electrode are both a material selected from the group consisting essentially of aluminum, copper, tungsten, titanium, a metal silicide, a conductive ceramic, doped silicon, and combinations thereof.

7. The integrated circuit of claim 1 wherein liner dielectric has a thickness of from about 5 nm to about 15 nm.

8. An integrated circuit comprising:

a dielectric layer having a first semiconductor fin therein and a second semiconductor fin therein;

a first recess in the dielectric layer above the first semiconductor fin and a second recess in the dielectric layer above the second semiconductor fin; and

a first electrode in the first recess above the first semiconductor fin and a second electrode physically isolated from the first electrode in the second recess above the second semiconductor fin, wherein no portions of the first electrode and the second electrode are disposed on sidewalls of the first semiconductor fin and the second semiconductor fin.

9. The integrated circuit of claim 8, wherein the first and second electrode are formed of a material selected from the group consisting essentially of a metal, a metal alloy, a conductive ceramic, a silicide, a doped semiconductor, and combinations thereof.

10. The integrated circuit of claim 8 further comprising:

a third semiconductor fin in the dielectric layer; and

a third electrode above the third semiconductor fin, the third electrode being electrically connected to the first electrode.

11. The integrated circuit of claim 10, further comprising:

a conductive line extending over the first, second and third semiconductor fins;

a first conductive via electrically connecting the conductive line to the first electrode;

and a second conductive via electrically connecting the conductive line to the third electrode.

12. The integrated circuit of claim 11, further comprising:

a second conductive line extending over the first, second and third semiconductor fins; and

a third conductive via electrically connecting the second conductive line to the second electrode.

13. The integrated circuit of claim 8 further, comprising a finFET semiconductor fin in the dielectric layer, the finFET semiconductor fin having a finFET formed therein.

14. The integrated circuit of claim 13, further comprising a third semiconductor fin in the dielectric layer having a third electrode above the third semiconductor fin, the third electrode being electrically connected to the first electrode.

15. The integrated circuit of claim 8, wherein the first recess and the second recess are lined with a dielectric liner.

16. The integrated circuit of claim 15, wherein the dielectric liner is selected from a group consisting of silicon oxide or a metal oxide of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu and mixtures thereof.

17. An integrated circuit, comprising:

a substrate having a top major surface;

a capacitor dielectric layer above the top major surface of the substrate, the capacitor dielectric layer having a first, a second and a third recess extending from a topmost surface of the capacitor dielectric layer to the substrate, wherein the second recess is between the first and third recesses;

a dielectric liner lining the first, the second and the third recesses;

a conductor material filling the lined first, second and third recesses, forming a first, a second and third electrode, respectively, the first, the second and the third electrodes extending substantially perpendicular to the top major surface of the substrate;

a first conductive line extending over the capacitor dielectric layer and the first, second and third electrodes, the first conductive line being electrically connected to the first and third electrodes; and

a second conductive line extending over the capacitor dielectric layer and the first, second and third electrodes, the second conductive line being electrically connected to the second electrode.

18. The integrated circuit of claim 17, further comprising a finFET fin extending from the top major surface of the substrate and a transistor formed in the finFET.

19. The integrated circuit of claim 17, wherein the dielectric liner is selected from a group consisting of silicon oxide or a metal oxide of Li, Be, Mg, Ca, Sr, Sc, Y, Zr, Hf, Al, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu and mixtures thereof.

20. The integrated circuit of claim 17, wherein liner dielectric has a thickness of from about 5 nm to about 15 nm.