Integrated Circuit Having a MOM Capacitor and Method of Making Same
First Claim
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1. An integrated circuit comprising:
- a capacitor, the capacitor includinga substrate;
a capacitor dielectric layer on a major surface of the substrate, the capacitor dielectric layer having a first recess and a second recess therein;
a first semiconductor fin extending from the major surface of the substrate within the first recess;
a first capacitor electrode within the first recess and atop the first semiconductor fin;
a second semiconductor fin extending from the major surface of the substrate and within the second recess; and
a second capacitor electrode within the second recess and atop the second semiconductor fin.
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Abstract
An integrated circuit can include a MOM capacitor formed simultaneously with other devices, such as finFETs. A dielectric layer formed on a substrate has a first semiconductor fin therein and a second semiconductor fin therein. Respective top portions of the fins are removed to form respective recesses in the dielectric layer. First and second electrodes are formed in the recesses. The first and second electrodes and the interjacent dielectric layer form a MOM capacitor.
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Citations
20 Claims
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1. An integrated circuit comprising:
a capacitor, the capacitor including a substrate; a capacitor dielectric layer on a major surface of the substrate, the capacitor dielectric layer having a first recess and a second recess therein; a first semiconductor fin extending from the major surface of the substrate within the first recess; a first capacitor electrode within the first recess and atop the first semiconductor fin; a second semiconductor fin extending from the major surface of the substrate and within the second recess; and a second capacitor electrode within the second recess and atop the second semiconductor fin. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. An integrated circuit comprising:
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a dielectric layer having a first semiconductor fin therein and a second semiconductor fin therein; a first recess in the dielectric layer above the first semiconductor fin and a second recess in the dielectric layer above the second semiconductor fin; and a first electrode in the first recess above the first semiconductor fin and a second electrode physically isolated from the first electrode in the second recess above the second semiconductor fin, wherein no portions of the first electrode and the second electrode are disposed on sidewalls of the first semiconductor fin and the second semiconductor fin. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16)
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17. An integrated circuit, comprising:
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a substrate having a top major surface; a capacitor dielectric layer above the top major surface of the substrate, the capacitor dielectric layer having a first, a second and a third recess extending from a topmost surface of the capacitor dielectric layer to the substrate, wherein the second recess is between the first and third recesses; a dielectric liner lining the first, the second and the third recesses; a conductor material filling the lined first, second and third recesses, forming a first, a second and third electrode, respectively, the first, the second and the third electrodes extending substantially perpendicular to the top major surface of the substrate; a first conductive line extending over the capacitor dielectric layer and the first, second and third electrodes, the first conductive line being electrically connected to the first and third electrodes; and a second conductive line extending over the capacitor dielectric layer and the first, second and third electrodes, the second conductive line being electrically connected to the second electrode. - View Dependent Claims (18, 19, 20)
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Specification