SELF-BIASED CHARGE PUMP

• US 20160233764A1
• Filed: 02/10/2015
• Published: 08/11/2016
• Est. Priority Date: 02/10/2015
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Park, Dongmin, Leung, Lai Kan, Park, Jong Min
• Granted Patent: US 9,473,022 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H03L 7/08 Details of the phase-locked loop
• CPC Class Codes: H03L 7/0895 Details of the current generators H03L7/0893 takes precedence

Abstract

An apparatus including: a current source configured to generate current; a switching current source circuit coupled to the current source and a first bias node to allow the current to flow through the switching current source circuit into the first bias node; a first bias circuit configured to receive a first control signal from a phase detector, the first bias circuit configured to mirror the current flowing through the switching current source circuit in response to the first control signal; a second bias circuit coupled to the first bias circuit at an output node and a second bias node, the second bias circuit configured to receive a second control signal from the phase detector; and a transconductance amplifier configured to receive a feedback signal from the output node and generate an output current to control the second biasing node.

Claims

1. An apparatus comprising:

a current source configured to generate current;

a switching current source circuit coupled to the current source and a first bias node to allow the current to flow through the switching current source circuit into the first bias node;

a first bias circuit configured to receive a first control signal from a phase detector, the first bias circuit configured to mirror the current flowing through the switching current source circuit in response to the first control signal;

a second bias circuit coupled to the first bias circuit at an output node and a second bias node, the second bias circuit configured to receive a second control signal from the phase detector; and

a transconductance amplifier configured to receive a feedback signal from the output node and generate an output current to control the second biasing node.

2. The apparatus of claim 1, wherein the apparatus is a charge pump of a phase-locked loop.

3. The apparatus of claim 1, wherein the first control signal is a down signal to draw the current out of the output node.

4. The apparatus of claim 1, wherein the second control signal is a complementary up signal to pump the current into the output node.

5. The apparatus of claim 1, wherein the switching current source circuit comprises a first transistor configured with a gate terminal coupled to the first bias node, a drain terminal coupled to the current source and the gate terminal, and a source terminal coupled to a ground voltage.

6. The apparatus of claim 5, further comprising a first capacitor coupled to the gate terminal of the first transistor and the ground voltage.

7. The apparatus of claim 6, wherein the first bias circuit comprises a second transistor and a third transistor, wherein the second and third transistors are configured with n-channel metal oxide semiconductor field-effect transistors (MOSFETs).

8. The apparatus of claim 7, wherein the second transistor is configured with a drain terminal coupled to the output node and a gate terminal coupled to the first bias node.

9. The apparatus of claim 8, wherein the third transistor is configured with a gate terminal to receive the first control signal, a drain terminal coupled to a source terminal of the second transistor, and a source terminal coupled to the ground voltage.

10. The apparatus of claim 9, wherein the second bias circuit comprises a fourth transistor and a fifth transistor, wherein the fourth and fifth transistors are configured with p-channel MOSFETs.

11. The apparatus of claim 10, wherein the fourth transistor is configured with a gate terminal coupled to the second bias node and a drain terminal coupled to the output node.

12. The apparatus of claim 11, wherein the fifth transistor is configured with a gate terminal to receive the second control signal, a drain terminal coupled to a source terminal of the fourth transistor, and a source terminal coupled to a supply voltage.

13. The apparatus of claim 12, further comprising a second capacitor coupled to the second bias node and the supply voltage.

14. An apparatus, comprising:

a current source configured to generate current;

a switching current source circuit coupled to the current source and a first bias node to allow the current to flow through the switching current source circuit into the first bias node;

a first bias circuit configured to receive a first control signal from a phase detector, the first bias circuit configured to mirror the current flowing through the switching current source circuit in response to the first control signal;

a second bias circuit coupled to the first bias circuit at an output node and a second bias node, the second bias circuit configured to receive a second control signal from the phase detector; and

a unity gain buffer having a positive input terminal, a negative input terminal, and an output terminal, the positive input terminal configured to receive an input signal, the negative input terminal coupled to the output terminal,

wherein the output terminal is coupled to the output node, the first bias circuit and the second bias circuit.

15. The apparatus of claim 14, wherein the first bias circuit comprises a second transistor and a third transistor, wherein the second and third transistors are configured with n-channel MOSFETs.

16. The apparatus of claim 15, wherein the output terminal of the unity gain buffer is coupled to a source terminal of the second transistor and a drain terminal of the third transistor.

17. The apparatus of claim 14, wherein the second bias circuit comprises a fourth transistor and a fifth transistor, wherein the fourth and fifth transistors are configured with p-channel MOSFETs.

18. The apparatus of claim 17, wherein the output terminal of the unity gain buffer is coupled to a source terminal of the fourth transistor and a drain terminal of the fifth transistor.

19. A phase-locked loop, comprising:

a phase detector configured to receive a reference signal and a divider output signal and output a control signal and a complementary control signal;

a charge pump comprising;

a current source configured to generate current;

a switching current source circuit coupled to the current source and a first bias node to allow the current to flow through the switching current source circuit into the first bias node;

a first bias circuit configured to receive a first control signal from a phase detector, the first bias circuit configured to mirror the current flowing through the switching current source circuit in response to the first control signal;

a second bias circuit coupled to the first bias circuit at an output node and a second bias node, the second bias circuit configured to receive a second control signal from the phase detector;

a transconductance amplifier configured to receive a feedback signal from the output node and generate an output current to control the second biasing node;

a low pass filter configured to receive the current pulse train signal and output a control voltage;

a voltage controlled oscillator configured to receive the control voltage and output a corresponding frequency signal; and

a frequency divider configured receive the corresponding frequency signal and output the divider output signal for feedback to the phase detector.

20. The phase-locked loop of claim 19, wherein the first bias circuit is a DN bias circuit and the second bias circuit is an UP bias circuit.