OPTICAL RECEIVER CHAIN FOR COMPONENTS OF A PHOTOPLETHYSMOGRAPH SIGNAL

• US 20160235313A1
• Filed: 08/27/2015
• Published: 08/18/2016
• Est. Priority Date: 02/13/2015
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Lee, Seung Bae, Li, Wen, Sharma, Ajit, Narayanan, Sriram, Ramaswamy, Srinath Mathur, Polley, Arup
• Granted Patent: US 9,717,426 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: A61B 2562/0238 Optical sensor arrangements for performing transmission measurements on body tissue
• CPC Class Codes: A61B 5/02427 Details of sensor
• CPC Class Codes: A61B 5/6826 Finger
• CPC Class Codes: A61B 5/7228 Signal modulation applied to the input signal sent to patient or subject; demodulation to recover the physiological signal modulation H03C

Abstract

The circuitry of an optical receiver reduces the ambient DC component and the pleth DC component to leave a pleth signal with substantially only a pleth AC component. The circuitry also provides gain control and can provide transmit power control to change the range of the pleth AC component to occupy a desired input range of an analog-to-digital converter.

Claims

1. Circuitry for an optical receiver, comprising:

a photo detector to;

receive ambient light that has an ambient intensity and, in response thereto, output a first signal on at least one first line having a first magnitude that represents the ambient intensity; and

receive pulsed light that has a pulsed intensity and, in response thereto, output a second signal on the at least one first line having a second magnitude that represents the pulsed intensity without the ambient intensity, the second magnitude of the second signal having a pleth DC component and a pleth AC component; and

a demodulation circuit coupled to the photo detector to;

sample and hold the first signal, and output a third signal on at least one second line whose magnitude represents the first magnitude of the first signal; and

sample and hold the second signal, and output a fourth signal on the at least one second line whose magnitude represents the second magnitude of the second signal, the magnitude of the fourth signal having a pleth DC component that represents the pleth DC component of the second signal, and a pleth AC component that represents the pleth AC component of the second signal.

2. The circuitry of claim 1 and further comprising a buffer coupled to the demodulation circuit, the buffer to:

receive the magnitude of the third signal, and output a pleth signal having a first magnitude that represents the magnitude of the third signal; and

receive the magnitude of the fourth signal, reduce the pleth DC component of the magnitude of the fourth signal by a defined amount to form the pleth signal having a second magnitude, and output the pleth signal having the second magnitude.

3. The circuitry of claim 2 and further comprising an analog-to-digital (A/D) converter coupled to the buffer, the A/D converter to:

digitize the first magnitude of the pleth signal to form a first digital word that represents the first magnitude of the pleth signal; and

digitize the second magnitude of the pleth signal to form a second digital word that represents the second magnitude of the pleth signal.

4. The circuitry of claim 3 and further comprising a controller coupled to the A/D converter, the photo detector, and the buffer, the controller to:

generate an ambient DC correction word that represents the ambient intensity in response to the first digital word, and output the ambient DC correction word to the photo detector; and

generate a pleth DC correction word that represents the defined amount in response to the second digital word, and output the pleth DC correction word to the buffer.

5. The circuitry of claim 4 wherein the photo detector is to generate the magnitude of the second signal by reducing a magnitude that represents the pulsed intensity by a magnitude that represents the ambient intensity as defined by the ambient DC correction word.

6. The circuitry of claim 4 wherein the buffer is to generate the second magnitude of the pleth signal by reducing a magnitude that represents the magnitude of the fourth signal by a magnitude that represents the pleth DC component as defined by the pleth DC correction word.

7. The circuitry of claim 4 wherein the photo detector includes:

a photo diode to generate a pair of IP differential currents having first magnitudes that vary in response to variations in the ambient intensity, and second magnitudes that vary in response to variations in the pulsed intensity;

an ambient DC correction circuit coupled to the photo diode to source and sink a pair of correction differential currents in response to the ambient DC correction word, the pair of correction differential currents combine with the pair of IP differential currents to reduce the second magnitudes of the pair of IP differential currents by an amount determined from the ambient DC correction word to form corrected magnitudes for the pair of IP differential currents; and

a transimpedance amplifier coupled to the ambient DC correction circuit to convert the pair of IP differential currents into a pair of VP differential voltages with first magnitudes that represent the first magnitudes of the pair of IP differential currents, and second magnitudes that represent the corrected magnitudes of the pair of IP differential currents.

8. The circuitry of claim 7 wherein the ambient DC correction circuit includes a pair of digital-to-analog (D/A) converters to receive the ambient DC correction word, and convert the ambient DC correction word into the pair of correction differential currents.

9. The circuitry of claim 7 wherein the first and second signals are output as the pair of VP differential voltages.

10. The circuitry of claim 7 wherein the demodulation circuit includes:

a first SH sub-circuit to sample and hold the first magnitudes of the pair of VP differential voltages, and output a pair of sampled differential voltages having first magnitudes that represent the first magnitudes of the pair of VP differential voltages, and

a second SH sub-circuit coupled to the first SH sub-circuit to sample and hold the second magnitudes of the pair of VP differential voltages, and output the pair of sampled differential voltages with second magnitudes that represents the second magnitudes of the pair of VP differential voltages.

11. The circuitry of claim 10 wherein the third and fourth signals are output as the pair of sampled differential voltages.

12. The circuitry of claim 10 wherein the buffer includes:

a D/A charge/voltage converter to generate a pair of correction differential charges/voltages having magnitudes in response to the pleth DC correction word; and

an amplifier coupled to the D/A charge/voltage converter to;

amplify the first magnitudes of the pair of sampled differential voltages to form the first magnitudes of a pair of pleth differential voltages; and

reduce a first value that represents the second magnitudes of the pair of sampled differential voltages by a second value that represents the magnitudes of the pair of correction differential charges/voltages to form the second magnitudes of the pair of pleth differential voltages.

13. The circuitry of claim 12 wherein the pleth signal is output as the pair of pleth differential voltages.

14. The circuitry of claim 1 wherein the pulsed intensity of the pulsed light includes a first pulsed intensity and a second pulsed intensity.

15. The circuitry of claim 1 wherein the photo detector includes two photodiodes.

16. The circuitry of claim 1 wherein

the photo detector to:

receive ambient light that has a second ambient intensity, and output a third signal on at least one first line having a third magnitude that represents the second ambient intensity; and

receive pulsed light that has a second pulsed intensity, and output a fourth signal on the at least one first line having a fourth magnitude that represents the second pulsed intensity without the second ambient intensity, the fourth magnitude of the fourth signal having a pleth DC component and a pleth AC component; and

the demodulation circuit to;

sample and hold the third magnitude of the third signal on the at least one first line, and output a fifth signal on the at least one second line whose magnitude represents the third magnitude of the third signal on the at least one first line, and

sample and hold the fourth magnitude of the fourth signal on the at least one first line, and output a sixth signal on the at least one second line whose magnitude represents the fourth magnitude of the fourth signal on the at least one first line, the magnitude of the sixth signal on the at least one second line having a pleth DC component and a pleth AC component.

17. The circuitry of claim 16 wherein the buffer is to:

receive the magnitude of the fifth signal on the at least one second line, and outputs the pleth signal having a third magnitude that represents the magnitude of the fifth signal on the at least one second line; and

receive the magnitude of the sixth signal on the at least one second line, reduce the pleth DC component in the magnitude of the sixth signal by a defined amount to form the pleth signal with a fourth magnitude, and outputs the pleth signal having the fourth magnitude.

18. A method of operating circuitry for an optical receiver, the method comprising:

receiving ambient light that has an ambient intensity and, in response thereto, outputting a first signal having a first magnitude that represents the ambient intensity;

receiving pulsed light that has a pulsed intensity and, in response thereto, outputting a second signal having a second magnitude that represents the pulsed intensity without the ambient intensity, the second magnitude of the second signal having a pleth DC component and a pleth AC component;

sampling and holding the first magnitude of the first signal, and outputting a third signal having a magnitude that represents the first magnitude of the first signal; and

sampling and holding the second magnitude of the second signal, and outputting a fourth signal with a magnitude that represents the second magnitude of the second signal, the magnitude of the fourth signal having a pleth DC component that represents the pleth DC component of the second signal, and a pleth AC component that represents the pleth AC component of the second signal.

19. The method of claim 18 and further comprising:

receiving the magnitude of the third signal, and outputting a pleth signal having a magnitude that represents the magnitude of the third signal; and

receiving the magnitude of the fourth signal, reducing the pleth DC component of the magnitude of the fourth signal by a defined amount to form the pleth signal with a second magnitude, and outputting the pleth signal having the second magnitude.

20. The method of claim 19 and further comprising:

digitizing the first magnitude of the pleth signal to form a first digital word that represents the first magnitude of the pleth signal; and

digitizing the second magnitude of the pleth signal to form a second digital word that represents the second magnitude of the pleth signal.