Test IP-Based A.T.E. Instrument Architecture

• US 20160238657A1
• Filed: 01/28/2016
• Published: 08/18/2016
• Est. Priority Date: 01/17/2012
• Status: Active Grant

• Current Assignee: Shanghai LING CE Electronics Technologies Company Limited, Shanghai LING Key Electronic Technology Company Limited
• Original Assignee: Test Evolution Corp.
• Inventors: Czamara, Allen, Paulsen, Ed, Alperovich, Lev
• Granted Patent: US 9,910,086 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G01R 31/2834 Automated test systems [ATE]; using microprocessors or computers G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736
• CPC Class Codes: G01R 31/31704 Design for test; Design verification concerning scan tests G01R31/318583; computer-aided design G06F30/00
• CPC Class Codes: G01R 31/31705 Debugging aspects, e.g. using test circuits for debugging, using dedicated debugging test circuits generation of test sequences therefor G01R31/31835, using scan test therefor G01R31/318544
• CPC Class Codes: G01R 31/31907 Modular tester, e.g. controlling and coordinating instruments in a bus based architecture
• CPC Class Codes: G01R 31/31908 Tester set-up, e.g. configuring the tester to the device under test [DUT], down loading test patterns

Abstract

A test system based on multiple instances of reconfigurable instrument IP specifically matched to the device under test may be used in integrating automated testing of semiconductor devices between pre-silicon simulation, post-silicon validation, and production test phases, in one embodiment of software and hardware across all three phases, for different devices. The reconfigurable test system comprises: a tester instrument, instances of instrument IP instantiated in the tester instruments, a computer system, and a test program. The tester instrument connects to a device under test (DUT), and includes FPGAs reconfigurable for the three testing phases. The computer system has a user interface, and a controller connected to the reconfigurable tester instrument via a data bus. The test program stored on the controller, and the controller, instantiates interfaces and protocols, and certain process transactions to support the protocols, into FPGAs, to match device interfaces for each DUT, to execute test sequences.

Claims

1. A reconfigurable test system configured to seamlessly integrate automated testing of semiconductor devices between a pre-silicon simulation test phase, a post-silicon validation test phase, and a production test phase, in one embodiment of software and hardware across all three of the test phases, for different devices, said reconfigurable test system comprising:

a tester instrument configured to be connected to a plurality of pins of a semiconductor device under test (DUT), said tester instrument comprising one or more FPGAs to thereby be reconfigurable, for use in the three phases of testing;

multiple instances of Instrument IP (IIP) matched to each of one or more specific interfaces of a given DUT to provide functional and performance validation, characterization, and production test capabilities;

a computer system configured with a user interface, said computer system comprising a controller, and configured to have said controller be connected to said reconfigurable tester instrument via a data bus;

a test program stored on said controller, said test program and controller configured, when said program is executed, to instantiate said multiple instances of IIP into said reconfigurable tester instrument to be matched to device interfaces for each different DUT, and configured to execute a sequence of tests utilizing the IIP;

an external memory;

a protocol engine, said protocol engine configured to maintain an interface protocol to and from the DUT;

a transaction processor, said transaction processor configured to take transactions from either said external memory or from a software executive, or to be algorithmically generated internally, and process and send them to said protocol engine;

said transaction processor further configured to synchronize usage events by said multiple instances of Instrument IP, and configured to log events to save time-stamped transactions including pin-level detail into and out of the DUT, for each pin of the semiconductor DUT, and to store a log of the time-stamped transactions in said external memory; and

a debug tool configured to graphically display the stored time-stamped pin-level transactions for each pin of the semiconductor DUT, both into and out of the DUT, and said debug tool further configured to compare said time-stamped transactions out of said pins to an expected response to help debug test cases and DUT errors, and said debug tool further configured to compare and display said transactions into and out of the DUT in a scoreboard format.

2. The reconfigurable test system according to claim 1 wherein said tester instrument is configured to be connected to the DUT using one or more of the following connections:

one or more pins of said one or more FPGAs in direct contact with the DUT interface;

a digital pin electronic circuit;

a signal conditioning circuit;

an analog-to-digital convertor;

a digital-to-analog convertor; and

a load board.

3. The reconfigurable test system according to claim 2 wherein said IIP comprises one or more interfaces and protocols, and process transactions to support said protocol;

and wherein said IIP is configured to transform data received from a protocol engine for compliance testing.

4. The reconfigurable test system according to claim 3 wherein a test layer and a scenario layer are configured to communicate with said tester instrument using an SCE-MI interface, to provide seamless integration between the pre-silicon simulation test phase and the post-silicon validation test phase, and wherein a test code used for stimulus and response checking of the DUT is thereby usable for both the pre-silicon simulation test phase and the post-silicon validation test phase.

5. The reconfigurable test system according to claim 4 wherein said multiple instances of instrument IP comprises native random stimulus generation and response checking.

6. The reconfigurable test system according to claim 5 wherein said multiple instances of instrument IP comprises a combination of random and pre-defined stimuli, and random and pre-defined response checking natively defined for each said multiple instances of instrument IIP for all DUT interfaces.

7. The reconfigurable test system according to claim 6 wherein said tester instrument is implemented as a monolithic integrated circuit.

8. The reconfigurable test system according to claim 6 wherein said tester instrument is implemented as a multi-chip module.