SEMICONDUCTOR INTEGRATED CIRCUIT
First Claim
1. A semiconductor integrated circuit comprising:
- an output transistor connected between a first node on an input terminal side and a second node on an output terminal side;
an error amplifier that has a non-inverting input terminal, an inverting input terminal, and an output terminal, the non-inverting input terminal being connected to a third node between the second node and a standard potential, the inverting input terminal being connected to a reference voltage, the output terminal being connected to the gate of the output transistor; and
a control circuit that makes responsiveness of the error amplifier at startup slower than responsiveness of the error amplifier at steady operation.
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Accused Products
Abstract
According to one embodiment, there is provided a semiconductor integrated circuit including an output transistor, an error amplifier, and a control circuit. The output transistor is connected between a first node on an input terminal side and a second node on an output terminal side. The error amplifier has a non-inverting input terminal, an inverting input terminal, and an output terminal. The non-inverting input terminal is connected to a third node between the second node and a standard potential. The inverting input terminal is connected to a reference voltage. The output terminal is connected to the gate of the output transistor. The control circuit makes responsiveness of the error amplifier at startup slower than responsiveness of the error amplifier at steady operation.
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Citations
20 Claims
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1. A semiconductor integrated circuit comprising:
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an output transistor connected between a first node on an input terminal side and a second node on an output terminal side; an error amplifier that has a non-inverting input terminal, an inverting input terminal, and an output terminal, the non-inverting input terminal being connected to a third node between the second node and a standard potential, the inverting input terminal being connected to a reference voltage, the output terminal being connected to the gate of the output transistor; and a control circuit that makes responsiveness of the error amplifier at startup slower than responsiveness of the error amplifier at steady operation. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A semiconductor integrated circuit comprising:
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an output circuit connected between a first node on an input terminal side and a second node on an output terminal side, circuit resistance between the first node and the second node being able to be switched; an error amplifier that has a non-inverting input terminal, an inverting input terminal, and an output terminal, the non-inverting input terminal being connected to a third node between the second node and a standard potential, the inverting input terminal being connected to a reference voltage, and the output terminal being connected to the output circuit; and a control circuit that makes circuit resistance of the output circuit at startup higher than circuit resistance of the output circuit at steady operation. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification