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CLOCKING FOR PIPELINED ROUTING

  • US 20160239043A1
  • Filed: 04/28/2016
  • Published: 08/18/2016
  • Est. Priority Date: 11/08/2013
  • Status: Abandoned Application
First Claim
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1. An integrated circuit, comprising:

  • a first clock selection stage that selects from a first plurality of clock signals and that outputs a second plurality of clock signals;

    a second clock selection stage that selects from the second plurality of clock signals that and that outputs a third plurality of clock signals; and

    pipelined routing resources that receive the third plurality of clock signals.

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