CLOCKING FOR PIPELINED ROUTING
First Claim
1. An integrated circuit, comprising:
- a first clock selection stage that selects from a first plurality of clock signals and that outputs a second plurality of clock signals;
a second clock selection stage that selects from the second plurality of clock signals that and that outputs a third plurality of clock signals; and
pipelined routing resources that receive the third plurality of clock signals.
0 Assignments
0 Petitions
Accused Products
Abstract
An integrated circuit may have pipelined programmable interconnects that are configured to select between a routing signal stored in a register and the identical routing signal bypassing the register. The pipelined programmable interconnect may send the selected routing signal over a wire to the next pipelined programmable interconnect circuitry. The integrated circuit may also have clock routing circuitry to select respective clock signals for the registers in the different pipelined programmable interconnects. The clock routing circuitry may include first interconnects that convey region clocks, second interconnects that conveys routing clocks, a first selector circuit to select routing clocks among the region clocks, and a second selector circuit to select routing clocks for the respective registers.
-
Citations
20 Claims
-
1. An integrated circuit, comprising:
-
a first clock selection stage that selects from a first plurality of clock signals and that outputs a second plurality of clock signals; a second clock selection stage that selects from the second plurality of clock signals that and that outputs a third plurality of clock signals; and pipelined routing resources that receive the third plurality of clock signals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
-
-
10. A method of operating an integrated circuit, comprising:
-
generating a plurality of region clocks; with a first clock selection stage, receiving the plurality of region clocks and outputting a plurality of routing clocks; with a second clock selection stage, receiving the plurality of routing clocks and outputting a plurality of selected clock signals; and receiving the plurality of selected clock signals at a plurality of pipelined routing resources. - View Dependent Claims (11, 12, 13, 14)
-
-
15. An integrated circuit, comprising:
-
a first functional block that includes a first group of pipelined routing resources; a second functional block that includes a second group of pipelined routing resources; and routing paths connecting the first functional block to the second functional block, wherein at least two pipelined routing resources in the first group receive a different number of clock signals. - View Dependent Claims (16, 17, 18, 19, 20)
-
Specification