BIT REMAPPING MECHANISM TO ENHANCE LOSSY COMPRESSION IN FLOATING-POINT APPLICATIONS

• US 20160239265A1
• Filed: 02/16/2015
• Published: 08/18/2016
• Est. Priority Date: 02/16/2015
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Duong, Nam, Mednick, Elliot, Zhang, DongPing
• Granted Patent: US 9,851,945 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence
• CPC Class Codes: H03M 7/24 Conversion to or from floating-point codes

Abstract

Methods and systems of reducing power transmitted over a memory to cache bus having a plurality of cache lines by identifying floating point numbers transmitted over a cache line, rounding bits in least significant bit (LSB) positions of identified floating point (FP) numbers to a uniform binary value string, mapping the rounded bits from the LSB positions to most significant bit (MSB) positions of each FP number to increase a chance of matching bit patterns between pairs of the FP numbers, and compressing the floating point numbers by replacing matched bit patterns with smaller data elements using a defined data compression process. A decompressor decompresses the compressed FP numbers using a defined decompression process corresponding to the defined compression process; and the mapping component applies a reverse mapping function to map the rounded bits back to original LSB positions from the MSB positions to recover the original floating point numbers.

Claims

1. A method for processing floating point numbers, comprising:

detecting floating point (FP) numbers in a dataset;

rounding bits in least significant bit (LSB) positions of each detected FP number to a set binary value; and

mapping the rounded bits from the LSB positions to most significant bit (MSB) positions of each detected FP number to increase a chance of matching bit patterns between pairs of detected FP numbers.

4. The method of claim 1 wherein the set binary value is zero and the LSB bits are rounded down.

5. The method of claim 1 wherein the set binary value is one and the LSB bits are rounded up.

6. The method of claim 1 wherein the mapping comprises at least one shift function and at least one hashing function.

10. The method of claim 1 wherein the detecting comprises one of:

using knowledge of a defined format of floating point numbers to determine the presence the floating point number, and recognizing a datatype identifier associated with the floating point number.

11. The method of claim 10 wherein the defined format comprises an IEEE-754 floating point representation.

2. The method of claim 2 further comprising compressing the detected FP numbers using a defined compression process.

7. The method of claim 2 wherein the defined compression process is selected from the group consisting of:

Frequent-Pattern Compression, X-match, X-RL, C-Pack, SSDPMC2, SSDPMC2+33, and MPack compression.

8. The method of claim 2 wherein the dataset is transmitted over a cache line to one of an L1 or L2 cache.

9. The method of claim 8 wherein the defined compression process comprises MPack compression, and wherein the mapping is configured to reduce power consumption requirements of transmitting the dataset over the cache line.

3. The method of claim 3 further comprising:

decompressing the compressed FP numbers using a defined decompression process corresponding to the defined compression process; and

applying a reverse mapping function to map the rounded bits back to original LSB positions from the MSB positions.

12. A method of reducing power transmitted over a memory to cache bus having a plurality of cache lines, the method comprising;

rounding bits in least significant bit (LSB) positions of floating point (FP) numbers to a uniform binary value string;

mapping the rounded bits from the LSB positions to most significant bit (MSB) positions of each FP number to increase a chance of matching bit patterns between pairs of the FP numbers; and

compressing the floating point numbers by replacing matched bit patterns with smaller data elements using a defined data compression process.

13. The method of claim 12 further comprising:

decompressing the compressed FP numbers using a defined decompression process corresponding to the defined compression process; and

applying a reverse mapping function to map the rounded bits back to original LSB positions from the MSB positions.

14. The method of claim 13 wherein the uniform binary value string is one of a sequence of zeros or a sequence of ones.

15. The method of claim 13 wherein the defined compression process is selected from the group consisting of:

Frequent-Pattern Compression, X-match, X-RL, C-Pack, SSDPMC2, SSDPMC2+33, and MPack compression.

16. The method of claim 12 further comprising identifying the floating point numbers within a variety of data types transmitted over the memory to cache bus, wherein the identifying comprises one of:

using knowledge of a defined format of floating point numbers to identify the floating point numbers amont the variety of data types, and recognizing a datatype identifier associated with the floating point numbers.

17. The apparatus of claim 16 further comprising:

a compressor compressing the detected FP numbers using a defined compression process

a decompressor decompressing the compressed FP numbers using a defined decompression process corresponding to the defined compression process; and

the mapping component applying a reverse mapping function to map the rounded bits back to original LSB positions from the MSB positions.

18. The apparatus of claim 17 wherein the defined compression process is selected from the group consisting of:

Frequent-Pattern Compression, X-match, X-RL, C-Pack, SSDPMC2, SSDPMC2+33, and MPack compression.

19. The apparatus of claim 16 wherein the dataset is transmitted over the cache line to one of an L1 or L2 cache.

20. The apparatus of claim 19 wherein the mapping is configured to reduce power consumption requirements of transmitting the dataset over the cache line.

16-1. An apparatus for of reducing power transmitted over a memory to cache bus having a plurality of cache lines, comprising:

a detection component detecting floating point (FP) numbers in a dataset transmitted over a cache line of the plurality of cache lines;

a rounding component rounding bits in least significant bit (LSB) positions of each detected FP number to a set binary value; and

a mapping component mapping the rounded bits from the LSB positions to most significant bit (MSB) positions of each detected FP number to increase a chance of matching bit patterns between pairs of detected FP numbers.