BIT REMAPPING MECHANISM TO ENHANCE LOSSY COMPRESSION IN FLOATING-POINT APPLICATIONS
First Claim
1. A method for processing floating point numbers, comprising:
- detecting floating point (FP) numbers in a dataset;
rounding bits in least significant bit (LSB) positions of each detected FP number to a set binary value; and
mapping the rounded bits from the LSB positions to most significant bit (MSB) positions of each detected FP number to increase a chance of matching bit patterns between pairs of detected FP numbers.
1 Assignment
0 Petitions
Accused Products
Abstract
Methods and systems of reducing power transmitted over a memory to cache bus having a plurality of cache lines by identifying floating point numbers transmitted over a cache line, rounding bits in least significant bit (LSB) positions of identified floating point (FP) numbers to a uniform binary value string, mapping the rounded bits from the LSB positions to most significant bit (MSB) positions of each FP number to increase a chance of matching bit patterns between pairs of the FP numbers, and compressing the floating point numbers by replacing matched bit patterns with smaller data elements using a defined data compression process. A decompressor decompresses the compressed FP numbers using a defined decompression process corresponding to the defined compression process; and the mapping component applies a reverse mapping function to map the rounded bits back to original LSB positions from the MSB positions to recover the original floating point numbers.
-
Citations
20 Claims
-
1. A method for processing floating point numbers, comprising:
-
detecting floating point (FP) numbers in a dataset; rounding bits in least significant bit (LSB) positions of each detected FP number to a set binary value; and mapping the rounded bits from the LSB positions to most significant bit (MSB) positions of each detected FP number to increase a chance of matching bit patterns between pairs of detected FP numbers. - View Dependent Claims (4, 5, 6, 10, 11)
-
- 2. The method of claim 2 further comprising compressing the detected FP numbers using a defined compression process.
-
3. The method of claim 3 further comprising:
-
decompressing the compressed FP numbers using a defined decompression process corresponding to the defined compression process; and applying a reverse mapping function to map the rounded bits back to original LSB positions from the MSB positions.
-
-
12. A method of reducing power transmitted over a memory to cache bus having a plurality of cache lines, the method comprising;
-
rounding bits in least significant bit (LSB) positions of floating point (FP) numbers to a uniform binary value string; mapping the rounded bits from the LSB positions to most significant bit (MSB) positions of each FP number to increase a chance of matching bit patterns between pairs of the FP numbers; and compressing the floating point numbers by replacing matched bit patterns with smaller data elements using a defined data compression process. - View Dependent Claims (13, 14, 15)
-
-
16. The method of claim 12 further comprising identifying the floating point numbers within a variety of data types transmitted over the memory to cache bus, wherein the identifying comprises one of:
- using knowledge of a defined format of floating point numbers to identify the floating point numbers amont the variety of data types, and recognizing a datatype identifier associated with the floating point numbers.
- View Dependent Claims (17, 18, 19, 20)
-
16-1. An apparatus for of reducing power transmitted over a memory to cache bus having a plurality of cache lines, comprising:
-
a detection component detecting floating point (FP) numbers in a dataset transmitted over a cache line of the plurality of cache lines; a rounding component rounding bits in least significant bit (LSB) positions of each detected FP number to a set binary value; and a mapping component mapping the rounded bits from the LSB positions to most significant bit (MSB) positions of each detected FP number to increase a chance of matching bit patterns between pairs of detected FP numbers.
-
Specification